Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

Supriya Aggarwal,Kavita Khare

doi:10.1155/2012/185784

Abstract

One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper.

Highlights

Window filtering techniques [1, 2] are commonly employed in signal processing paradigm to limit time and frequency resolution
The CORDIC algorithm [8,9,10] inherently suffers from latency issues and using two CORDIC processors in series, as is done in [6, 7]; the overall latency of the system is hampered
The circuit consists of theta generator unit (TGU), window coefficient multiplier (WCM), circular CORDIC processor (CCP) and FIFO

Summary

Introduction

Window filtering techniques [1, 2] are commonly employed in signal processing paradigm to limit time and frequency resolution. The conventional hardware implementation of window functions uses lookup tables which give rise to various area and time complexities with increase in word lengths. They do not allow user-defined variations in the window length. An efficient implementation of flexible and reconfigurable window functions using CORDIC algorithm is suggested in [6, 7] Though they allow user-defined variations in window length, latency is a major problem. We replace the linear CORDIC processors used in the existing design by shift-add tree derived using Booth multiplication These modifications scale down the area consumption of the window architecture, with decrease in the number of pipeline stages.

Background

Redesigned-Scale-Free CORDIC Algorithm

Architecture for Implementing Window Functions

FPGA Implementation and Complexity Issues

Findings

Conclusion