Single Precision Multiplication Research Articles

COMPARATIVE OF RIVEST-SHAMIR-ADLEMAN CRYPTOSYSTEM AND ITS FOUR VARIANTS USING RUNNING TIME AND MEMORY CONSUMPTION ANALYSIS

The Rivest-Shamir-Adleman (RSA) algorithm, known for its slow single-precision multiplication (spm) and overall running time, is not commonly employed to encrypt user data directly. As a result, several researchers have developed various RSA-based cryptosystems to enhance the algorithm's performance while maintaining security. This paper presents a comparative analysis of different variants of the RSA cryptosystem, focusing on five specific cryptosystems: RSA, Somsuk-RSA, Modified-RSA (MRSA), Easy Simple Factoring-RSA (ESF-RSA), and Phony-RSA. The methodology involves evaluating the theoretical running time and memory usage through single-precision multiplication (spm) measurements, while the actual running time is estimated using Maple programming. The research has two primary objectives. Firstly, they examined each algorithm of the RSA variants and analysed them according to the proposed methodology. Secondly, to determine which cryptosystem consumes the most time and memory for key generation, encryption, and decryption. The results indicate that ESF-RSA and RSA are the fastest in terms of key generation, ESF-RSA is the quickest for encryption, and Phony-RSA excels in decryption speed. Additionally, ESF-RSA demonstrates the lowest memory usage, whereas MRSA requires the highest memory allocation for all processes.

A Combined Single Trace Attack on Global Shuffling Long Integer Multiplication and its Novel Countermeasure

Advanced collision-based single trace attacks which can be applied on simple power analysis resistant scalar multiplications become virtual threat on elliptic curve cryptosystems recently as their practical experimental results are increasingly reported in the literature. Since such attacks are based on detecting collisions of data dependent leakage caused by underlying long integer multiplications, so-called global shuffling countermeasure which breaks such collision correlation by independently randomizing the execution order of unit operations such as single precision multiplication and carry propagation, is considered as promising countermeasure if theoretical randomness of shuffling order is guaranteed. In this paper, we firstly analyze the practical security of the global shuffling long integer multiplications by exhibiting a combined single trace attack on software implementations on an ARM Cortex-M4 microcontroller. Our combined attack consists of a simple power analysis for revealing random permutation vectors which enables later collision-based single trace attack. First we demonstrate how to reveal random permutation vectors for carry propagation process of whole global shuffling long integer multiplications within a single power trace by simple power analysis accompanied with straightforward substitution of power consumption samples. Then we perform collision-based single trace attacks after rearranging the order of subtraces for unit carry propagations based on revealed permutation vectors. Since the vulnerability to simple power analysis is originated from the if-statement for selection of proper entries of the permutation vectors, we propose a novel countermeasure which eliminates such selection with simple addition and modulus operation and also demonstrate practical result achieving regularity in power trace patterns.

A comment on “An efficient common-multiplicand-multiplication method to the Montgomery algorithm for speeding up exponentiation”

In 2009, Wu proposed a fast modular exponentiation algorithm and claimed that the proposed algorithm on average saved about 38.9% and 26.68% of single-precision multiplications as compared to Dussé–Kaliski’s Montgomery algorithm and Ha–Moon’s Montgomery algorithm, respectively. However, in this comment, we demonstrate that Wu’s algorithm on average reduces the number of single-precision multiplications by at most 22.43% and 6.91%, when respectively compared with Dussé–Kaliski’s version and Ha–Moon’s version. That is, the computational efficiency of Wu’s algorithm is obviously overestimated.

An efficient common-multiplicand-multiplication method to the Montgomery algorithm for speeding up exponentiation

The modular exponentiation is a common operation for scrambling secret data and is used by several public-key cryptosystems, such as the RSA scheme and DSS digital signature scheme. However, the calculations involved in modular exponentiation are time-consuming especially when performed in software. In this paper, we propose an efficient CMM–MSD Montgomery algorithm by utilizing the Montgomery modular reduction method, common-multiplicand-multiplication (CMM) method, and minimal-signed-digit (MSD) recoding technique for fast modular exponentiation. By using the technique of recording the common signed-digit representations in the grouped substrings of exponent, our algorithm can improve the efficiency of both the original CMM exponentiation algorithm and the Montgomery multiplication algorithm. The fast modular exponentiation algorithm developed in this paper can be easily implemented in general signed-digit computing machine, and is therefore well suited for parallel implementation to fast evaluating modular exponentiation. Moreover, by using the proposed CMM–MSD Montgomery algorithm, on average the total number of single-precision multiplications can be reduced by about 38.9% and 26.68% as compared with Dusse–Kaliski’s Montgomery algorithm and Ha–Moon’s Montgomery algorithm, respectively.

Dual-mode floating-point multiplier architectures with parallel operations

Although most modern processors have hardware support for double precision or double-extended precision floating-point multiplication, this support is inadequate for many scientific computations. This paper presents the architecture of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware than a fully parallel quadruple precision multiplier. With this architecture, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have latencies of only two cycles. The multiplier is pipelined so that two double precision multiplications can begin every cycle or a quadruple precision multiplication can begin every other cycle. The technique used for the dual-mode quadruple precision multiplier is also applied to the design of a dual-mode double precision floating-point multiplier that performs a double precision multiplication or two single precision multiplications in parallel. Synthesis results show that the dual-mode double precision multiplier requires 43% less area than a conventional double precision multiplier. The correctness of all the multipliers presented in this paper is tested and verified through extensive simulation.

Memory latency consideration for load sharing on heterogeneous network of workstations

Although most modern processors have hardware support for double precision or double-extended precision floating-point multiplication, this support is inadequate for many scientific computations. This paper presents the architecture of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hard-ware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hard-ware than a fully parallel quadruple precision multiplier. With this architecture, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have latencies of only two cycles. The multiplier is pipelined so that two double precision multiplications can begin every cycle or a quadruple precision multiplication can begin every other cycle. The technique used for the dual-mode quadruple precision multiplier is also applied to the design of a dual-mode double precision floating-point multiplier that performs a double precision multiplication or two single precision multiplications in parallel. Synthesis results show that the dual-mode double precision multiplier requires 43% less area than a conventional double precision multiplier. The correctness of all the multipliers presented in this paper is tested and verified through extensive simulation.

An Efficient Montgomery Exponentiation Algorithm for Cryptographic Applications

Efficient computation of the modular exponentiations is very important and useful for public-key cryptosystems. In this paper, an efficient parallel binary exponentiation algorithm is proposed which based on the Montgomery multiplication algorithm, the signed-digit-folding (SDF) and common-multiplicand-multiplicand (CMM) techniques. By using the CMM technique of computing the common part from two modular multiplications, the same common part in two modular multiplications can be computed once rather twice, we can thus improve the efficiency of the binary exponentiation algorithm by decreasing the number of modular multiplications. By dividing the bit pattern of the minimal-signed-digit recoding exponent into three equal length parts and using the technique of recording the common parts in the folded substrings, the proposed SDF-CMM algorithm can improve the efficiency of the binary algorithm, thus can further decrease the computational complexity of modular exponentiation. Furthermore, by using the proposed parallel SDF-CMM Montgomery binary exponentiation algorithm, on average the total number of single-precision multiplications can be reduced by about 61.3% and 74.1% as compared with Chang-Kuo-Lin's CMM modular exponentiation algorithm and Ha-Moon's CMM Montgomery modular exponentiation algorithm, respectively.

A dual precision IEEE floating-point multiplier

A new algorithm for computing IEEE-compliant rounding is presented, called injection-based rounding. Injection-based rounding is simple and facilitates using the same rounding circuitry for different precisions. We demonstrate the usefulness of injection-based rounding in a design of an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. The multiplier is designed to minimize hardware cost by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions. The latency of the multiplier is in single-precision two clock cycles and in double precision the latency is three clock cycles, where each pipeline stage contains roughly 15 logic levels.

A common-multiplicand method to the montgomery algorithm for speeding up exponentiation

A common-multiplicand method to the Montgomery algorithm makes an improvement in speed when right-to-left binary exponentiation is applied. The idea is that the same common part in two modular multiplications can be computed once rather than twice. It reduces the overall number of single-precision multiplications by about 16%, compared to exponentiation with the Montgomery algorithm.

Partial double precision with residue retention: a new approach to solving differential equations on microprocessors

This paper proposes the use of partial double and triple precision with residue retention as a new arithmetic structure for solving differential equations on microprocessors. It is shown that a residue register, which is the distinguishing feature of the digital differential analyser, improves solution accuracy considerably by suppressing the accumulation of roundoff error, which is generally a problem on short-wordlength machines. Both theory and simulation reveal that by employing partial triple precision with residue retention, better than double-precision accuracy may be achieved with only a single-precision multiplication, whereas, without residue retention, single-precision accuracy only is possible.

Partial double precision with residue retention: a new approach to solving differential equations on microprocessors

This paper proposes the use of partial double and triple precision with residue retention as a new arithmetic structure for solving differential equations on microprocessors. It is shown that a residue register, which is the distinguishing feature of the digital differential analyser, improves solution accuracy considerably by suppressing the accumulation of roundoff error, which is generally a problem on short-wordlength machines. Both theory and simulation reveal that by employing partial triple precision with residue retention, better than double-precision accuracy may be achieved with only a single-precision multiplication, whereas, without residue retention, single-precision accuracy only is possible.