Single Precision Floating Point Unit Research Articles

CONTROL STRATEGY FOR REGENERATIVE BRAKING IN ELECTRIC VEHICLES

Abstract—In this paper, a high-speed 32-bit single precision Floating Point Unit (FPU) using Vedic mathematics is proposed. In a general processor, the division architecture plays a crucial role in deciding the overall speed of the system. However, the standard algorithms are sequential units and reduce the performance of the processor. Vedic Mathematics onthe other hand offers a new holistic approach to realizing these operations in a combinational unit. In the proposed architecture an optimized binary division architecture using Nikhilam Sutra is realized. The proposed method is coded in Verilog High Description Language (HDL), synthesized for Artix 7 Field-Programmable Gate Array (FPGA) board, and simulated using Xilinx Vivado Design Suite. Keywords:-Floating- points, Vedic maths, Nikhilam Sutra.

Online Signature Verification Systems on a Low-Cost FPGA

This paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision floating-point IEEE 754 format. The double-precision computations are replaced by simpler formats, without affecting the biometrics performance, in order to permit efficient implementations on low-cost FPGA families. The first approach is an embedded system based on MicroBlaze, a 32-bit soft-core microprocessor designed for Xilinx FPGAs, which can be configured by including a single-precision floating-point unit (FPU). The second implementation attaches a hardware accelerator to the embedded system to reduce the execution time on floating-point vectors. The last approach is a custom computing system, which is built from a large set of arithmetic circuits that replace the floating-point data with a more efficient representation based on fixed-point format. The latter system provides a very high runtime acceleration factor at the expense of using a large number of FPGA resources, a complex development cycle and no flexibility since it cannot be adapted to other biometric algorithms. By contrast, the first system provides just the opposite features, while the second approach is a mixed solution between both of them. The experimental results show that both the hardware accelerator and the custom computing system reduce the execution time by a factor ×7.6 and ×201 but increase the logic FPGA resources by a factor ×2.3 and ×5.2, respectively, in comparison with the MicroBlaze embedded system.

Implementation of a 32 – bit RISC processor with floating point unit in FPGA platform

With the ever-growing trends in the latest technologies, digital signal processing is one of the known platforms which is used for many applications. RISC processor is the main element in all high-speed digital signal processing applications. The aim is to develop a RISC processor by including a single precision floating point unit in the instruction set along with other instructions and a complex multiplication instruction as it is commonly used in the DSP application. The floating-point unit is written according to the IEEE 754 standard and to introduce Vedic mathematics concept to compare and estimate the performance in terms of delay. The idea is to provide an optimized floating-point arithmetic unit and thereby provide an additional feature for the RISC processor instruction set. By using the Vedic multiplier, the delay is reduced by 55% compared to the normal array multiplier. The entire design is coded in Verilog HDL simulated on Xilinx ISE 14.7 platform.

A Decomposition Workflow for Integrated Circuit Verification and Validation

This paper reviews a developed integrated circuit (IC) decomposition workflow that can be leveraged for extracting design files and performing advanced verification and validation techniques on fabricated chips. In this work, a commercial 130-nm microcontroller is delayered and imaged to recreate the full design stack-up. Using MicroNet’s Pix2Net, the features for each layer are extracted allowing a GDSII file to be generated and design netlists for target components to be recovered. The full decomposition process is executed on both the read only memory (ROM) array and universal serial communications interface (USCI) of the microcontroller to recover the layout GDSII and circuit netlist. A single-precision floating point unit (FPU) test article is used to incorporate a spectrum of error types into the design layout, thus creating a set of test articles with obfuscated errors. Once the netlists for each of the modified designs are extracted, formal verification techniques are applied to each netlist, thus illuminating the errors originally inserted into the layout. The extracted netlists are then converted into register transfer level (RTL) representations and simulated with the original design verification testbench.

Processor Design Using 32 Bit Single Precision Floating Point Unit

Processor Design Using 32 Bit Single Precision Floating Point Unit

Design of Out-of-Order Floating-Point Unit

Objective: Field Programmable Gate Arrays (FPGAs) are often used to accelerate hardware systems by implementing algorithms on hardware. This paper presents the design and implementation of a fully pipelined single-precision Floating-Point Unit (FPU) on a Spartan-6 FPGA chip. Methods: This paper presents a high-speed, modular design for improving the performance of such applications. While the proposed design is capable of performing basic arithmetic operations and square-root extraction, its modularity enables designers to add more functionality easily; or remove modules that they deem unnecessary for a particular application. Findings: The investigation shows that the adder and multiplier modules can be clocked at over 300 MHz and the top-module at over 200 MHz High operating frequencies were achieved by pre-computing possible values in earlier pipelining stages, then correcting results in later pipelining stages. It was also found that splitting longer operations in the critical path is a better alternative than processing the whole operation at once. Limiting “Max_Fanout”, an attribute provided by Xilinx XST tool, proved valuable in reducing delays on overloaded nets. Applications: This FPU would be a worthwhile addition as a floating-point extension in fixed-point processors for applications such as spectrum analyzers, 3D graphics, and audio processing units.

MDGRAPE-4: a special-purpose computer system for molecular dynamics simulations.

We are developing the MDGRAPE-4, a special-purpose computer system for molecular dynamics (MD) simulations. MDGRAPE-4 is designed to achieve strong scalability for protein MD simulations through the integration of general-purpose cores, dedicated pipelines, memory banks and network interfaces (NIFs) to create a system on chip (SoC). Each SoC has 64 dedicated pipelines that are used for non-bonded force calculations and run at 0.8 GHz. Additionally, it has 65 Tensilica Xtensa LX cores with single-precision floating-point units that are used for other calculations and run at 0.6 GHz. At peak performance levels, each SoC can evaluate 51.2 G interactions per second. It also has 1.8 MB of embedded shared memory banks and six network units with a peak bandwidth of 7.2 GB s−1 for the three-dimensional torus network. The system consists of 512 (8×8×8) SoCs in total, which are mounted on 64 node modules with eight SoCs. The optical transmitters/receivers are used for internode communication. The expected maximum power consumption is 50 kW. While MDGRAPE-4 software has still been improved, we plan to run MD simulations on MDGRAPE-4 in 2014. The MDGRAPE-4 system will enable long-time molecular dynamics simulations of small systems. It is also useful for multiscale molecular simulations where the particle simulation parts often become bottlenecks.

Design and Implementation of Area Efficient Single Precision Floating Point Unit

A floating-point unit (FPU) is a part of a computer system specially designed to carry out operations on floating point numbers. Floating point representation can support a much wider range of values than fixed point representation. This paper presents high speed FPGA implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, division functions on 32-bit operands that use the IEEE 754-2008 standard. The amount of hardware used in the single architecture is found to be less than the sum of hardware required in individual floating point units. All four individual units are implemented using VHDL and than one single unit is designed named floating point unit which can perform all the four operations. The code is dumped into vertex-5 FPGA.

The Implementation of High-speed Floating-point DBF Based on FPGA

In this paper, an implementation of high-speed floating-point digital beamformer on FPGA is proposed to implement 64 beams and 16 sensors of 50kHz linear array in multibeam echosounder. This implementation is based on single precision floating-point units for the accurate computation. Proposed pipelined architectures decrease the chip area requirements and cause to increase the throughput of the digital beamformer. Comparison of the proposed approach with another approach based on the Xilinx IP core generator modules shows that the former technique outperforms the latter in terms of latency and speed. The implemented digital beamformer achieved throughput rates more than 313MHz on Xilinx Virtex-4 series FPGA.

A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a CELL Processor

The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single-instruction multiple-data (SIMD) unit designed to accelerate media and data streaming with 128-bit operands. It supports 32-bit single-precision floating-point and 16-bit integer operands with two different latencies, six-cycle and seven-cycle, with 11 FO4 delay per stage. The FPU optimizes the performance of critical single-precision multiply-add operations. Since exact rounding, exceptions, and de-norm number handling are not important to multimedia applications, IEEE correctness on the single-precision floating-point numbers is sacrificed for performance and simple design. It employs fine-grained clock gating for power saving. The design has 768K transistors in 1.3 mm/sup 2/, fabricated SOI in 90-nm technology. Correct operations have been observed up to 5.6 GHz with 1.4 V and 56/spl deg/C, delivering 44.8 GFlops. Architecture, logic, circuits, and integration are codesigned to meet the performance, power, and area goals.