Single Precision Floating Point Multiplier Research Articles

Logic Design and Power Optimization of Floating-Point Multipliers.

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symbolic expansion idea, and the partial product caused by single-precision floating-point multiplication and the accumulation of partial products are optimized, and the flowing water is used to improve the throughput. Based on this, a series of verification and synthesis simulations are performed using the SMIC-7 nm standard cell process. It is verified that the new single-precision floating-point multiplier can achieve a smaller power share compared to the conventional single-precision floating-point multiplier.

Improvised hierarchy of floating point multiplication using 5:3 compressor

ABSTRACT The main objective is to develop floating-point multiplication (FPM) using 5:3 compressor based Vedic multiplier (VM), Karatsuba algorithm (KA) and canonical signed digit (CSD) algorithm to overcome the drawbacks presented in conventional compressor based FPM. In this scenario, an attempt is made to enhance the performance of FPM using three efficient algorithms. Finally, the performance analysis in terms of area, delay and power dissipation of using VM, KA and CSD with 5:3 compressor are examined and compared. The designs f00which are involved in mantissa multiplication are coded in Verilog HDL and implemented using Xilinx Vivado. It is clearly convinced from the 5:3 compressor based CSD that it provides better performance than other two algorithms by achieving acceptable area and delay. Single precision floating point multiplication (SPFPM) using Vedic with 5:3 compressor requires 29% Look Up Table (LUT) area and 30% slice area improvement in comparing with KA. In case of delay, KA gives 35% improvement compared to vedic based SPFPM. For CSD algorithm based SPFPM requires 46% improvement in LUTs area and 49% improvement in Slice area compared to KA based SPFPM.

Acceleration Techniques using Reconfigurable Hardware for Implementation of Floating Point Multiplier

A multiplier plays a vital part in multimedia and digital signal processors. The integer unit alone cannot achieve the desired computational speed required by modern applications. Unit specially designed to carry out operations on floating point numbers is required also commonly known as floating-point unit. The IEEE 754 standard is used for defining the format of floating point number which is widely accepted. Basically, two formats are used for representing the floating point numbers, single precision which works on 32- bit floating point numbers whereas double precision working on 64 bit. Though the number of bits on which double precision operates doubles as compared to single precision number, it is hardly used due to its requirement of very large memory and also the delay generated for the IEEE-754 standard floating point multiplication. This is the mojor reason for its rare implementation in designs requiinge high computing speed.[1] In this paper we are proposing three efficient algorithms for enhancing the speed and optimizing the area required for implementing single precision floating point multiplication. Also compared the results in terms of power dissipation, execution time and area requirement for the implementation with the conventional methods used. Here the algorithms are implemented and analyzed by using the most popular semi-custom design tool Vivado ISE 2015 and is synthesized by using Artix-7 FPGA and the same is reflected in the mathematical model purposed for each circuit.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors

FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors

An Efficient Single Precision Floating Point Multiplier Architecture based on Classical Recoding Algorithm

Background: Floating point (FP) multiplication has found its importance in many microprocessors but it is very difficult to implement on FPGA because of its complicated internal computation. Methods: We investigate partial product (PP) reduced FP multiplication based on Radix-4 Booth Encoded Algorithm (BEA). Radix-4 BEA reduces the number of PP generation by half. PP reduction performed in three steps such as Grouping bits (3-bit for each group), Encode the group and PP calculation for each group. Findings: The investigation results show that Radix-4 BEA works perfectly on signed multiplication and unsigned (FP mantissa) multiplication needs some extra consideration. Radix-4 BEA grouping multiplier bits need overlapping one bit from both adjacent group that limits block and parallel processing. 2’s complement calculation and sign extension essential for PP generation that increases the resource utilization. In this paper, 32 bit improved FP multiplication based on classical recoding and parallel processing method is proposed. Classical recoding reduces PP generation by half without overlapping, sign extension and 2’s complement. 24 bit mantissa split into blocks (8 bit each) and each blockis recoded using classical recoding algorithm and all blocks are performed in parallel. Applications: The experimental results show that our proposed design runs with high frequency with less resource utilization and suitable for signal processing applications.

English

English

NULL convention floating point multiplier.

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics

This work proposes designing of high speed floating point multipliers. The multipliers are designed using Vedic Mathematics. The Vedic Multiplier (VM) has a regular structure therefore can be easily layout in a Silicon chip. Two different VMs are designed with different adder structures viz. Ripple Carry Adder (RCA) and Carry Look-ahead Adder (CLA). A single precision floating point multiplier is designed with these two VM structures. The multipliers are structurally modeled in Verilog HDL. The simulation and synthesis are done in Xilinx® ISE 14.2. A comparison on the basis of area, power and delay is performed on Virtex-5 (xc5vlx110tff1136-1).

DESIGN OF A REVERSIBLE FUSED 32-POINT RADIX -2 FLOATING POINT FFT UNIT USING 3:2 COMPRESSOR

This paper aims on the design of a reversible fused 32Point Radix-2 single precision floating point FFT unit using 3:2 compressor. The work focuses on the realization of three reversible fused floating point units: reversible floating point add-sub unit, reversible floating point multiply-add unit and reversible floating point multiply-subtract unit. The proposed work requires the design of a reversible single precision floating point adder, a reversible single precision floating point subtractor and a reversible single precision floating point multiplier. A reversible single precision floating point adder and subtractor is designed with less quantum cost, less number of reversible gates and less constant inputs. A reversible single precision floating point multiplier is implemented using 3:2 compressor as the 24x24 bit multiplier based on 3:2 compressor is highly efficient when compared with the design using 4:3 compressors. A reversible fused 32-Point Radix-2 floating point FFT Unit using 3:2 compressor consumes less number of resources, operates at a slightly greater speed and dissipates less power when compared with the reversible discrete 32-Point Radix-2 floating point FFT Unit. The proposed Fused 32-Point Radix-2 floating point FFT unit using 3:2 compressor dissipates 2.074W while the same design as a discrete implementation dissipates 2.176W.

Improved Floating Point Multiplier Design based on Canonical Sign Digit 22

Improved floating point (FP) multiplier based on canonical signed digit code (CSDC) has been reported in this paper. Array structure was implemented through Hatamain’s scheme of partial product generation along with Baugh-Wooley’s (B.W) sign digit multiplication technique. Moreover, CSDC approaches were used for the addition of partial products in constant time without carry propagation and independent of operands. The functionality of these circuits was checked and performance parameters, such as propagation delay, dynamic switching power consumptions were calculated by spice spectre using 90nm CMOS technology. Implementation methodology ensures the stage reduction for floating point multiplier, hence substantial reduction in propagation delay compared with B.W.’s methodology, has been investigated. Implementation result offered propagation delay of the single precision floating point multiplier was only ~14.7ns propagation delay while the power consumption of the same was ~23.7mW. Almost ~40% improvement in speed from earlier reported FP multiplier, e.g. B.W implementation methodology, the best architecture reported so far, has been achieved.

A Low Power Design of Single Precision Floating Point Multiplier for Computing Techniques

A design and implementation of a 32 bit fast floating point multiplier with the single precision IEEE 754-2008 standard target for Xilinx virtex-5 FPGA. The proposed design and timing information of the multiplier sub-module has been calculated and the proposed design intends to increase the speed on the multiplier by reducing delay at every stage using optimal adder design. The proposed multiplier is made to multiply two floating point numbers and generate the output to make minimum time delay. The modules have been written in verilog HDL and it is simulated using the Xilinx ISE12.1 targeted on the FPGA.

HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES

In this paper, single-precision floating-point IEEE-754 standard Adder/Subtractor and Multiplier modules with high speed and area efficient are presented. These modules are designed, simulated, synthesized, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of normalization unit at the singleprecision floating-point multiplier and adder/Subtractor modules on the area, and speed is explained.