Abstract
In this paper, single-precision floating-point IEEE-754 standard Adder/Subtractor and Multiplier modules with high speed and area efficient are presented. These modules are designed, simulated, synthesized, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of normalization unit at the singleprecision floating-point multiplier and adder/Subtractor modules on the area, and speed is explained.
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