Abstract
Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.
Highlights
Clocked circuits have dominated semiconductor industry for the past two decades
The VHDL gate level structural model of the NULL convention logic (NCL) floating point multiplier (FPM) was designed using gate delays based on physical-level simulations with TSMC 1.8 V 0.18 μm static CMOS technology libraries [16]
The NCL FPM is compared with the synchronous FPM in terms of power, speed, and area using the synthesis results obtained from cadence
Summary
Clocked circuits have dominated semiconductor industry for the past two decades. Excessive clock skew, clock noise, and larger power dissipation of clocked circuits have led the way to the asynchronous world of very large scale integration (VLSI). NCL based asynchronous designs provide a significant contribution in the research of low power VLSI. We propose the design and characterization of a NCL based floating point multiplier (FPM) that is compliant with single precision IEEE 754. The proposed NCL FPM is targeted to perform multiplication of floating point numbers and to dissipate lower power when compared to its synchronous counterpart. The primary contribution of our research was to develop a low power and high precision, reusable NCL floating point multiplier library component, which in future can be used as an integral component in the design of NCL based DSP processor cores.
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