Single-port SRAM Research Articles

Impact of total ionizing dose on the alpha-soft error rate in FDSOI 28 nm SRAMs

Synergy effect of total ionizing dose (TID) on alpha-soft error rate (α-SER) in FDSOI 28 nm SRAM has been experimentally characterized using a dedicated setup combining alpha-particle irradiation (241Am solid source) in vacuum chamber and 10 keV X-ray irradiation. Measurements have been performed on a 3 Mbit single-port SRAM cut powered at 1 V. Irradiations up to 125 krad(Si) have been achieved and their impact on the α-SER has been characterized from the cumulated number of bitflips as a function of the exposition time to the alpha-source. Modelling and simulation have been used to link transistor threshold voltage variations to SRAM cell stability in terms of static noise margin (SNM), critical charge (Qcrit) and finally estimated SER, in good agreement with experimental results.

Single-Event Upsets for Single-Port and Two-Port SRAM Cells at the 5-nm FinFET Technology

Single-event cross sections of single-port and two-port SRAM designs are presented at the 5-nm node for alpha particles, 14-MeV neutrons, thermal neutrons, and heavy ions for reduced and nominal supply voltages. Single-port SRAM shows higher susceptibility with low LET particles at nominal operating voltages. However, circuit and parasitic differences in designs lead to the two-port design having higher susceptibility to high LET particles. The stronger dependence of two-port SRAM on particle LET is due to the increased contribution of diffusion current to overall charge collection. The increased number of fins connected to a storage node for the two-port design significantly increases diffusion charge collection and SEU cross-section, despite increased critical-charge and cell size.

Evaluation of the Single-Event-Upset Vulnerability for Low-Energy Protons at the 7- and 5-nm Bulk FinFET Nodes

Upsets due to low-energy protons are a concern for highly scaled technology nodes as critical charges for storage cells continue to decrease. This work evaluates the SEU vulnerability of D-FF and SRAM designs at the 7-nm and 5-nm bulk FinFET nodes. D-FF designs at the 5-nm node have single-event upset (SEU) cross-sections that are an order of magnitude greater than that of the 7-nm node due to unbalanced decreases in critical charge and collected charge. Upsets were observed for a wider range of proton energies for the 5-nm node than the 7-nm node D-FFs due to the decreases in critical charge and changes in fin geometry with scaling. Despite its smaller cell size, the single-port SRAM design was more susceptible than the two-port SRAM design due to the lower critical charge. Multi-cell upsets due to lower-energy protons were observed for the first time for SRAM designs at the 5-nm node. The results of this study indicate that designers will need to be mindful of SEUs for environments with significant fluxes of low-energy protons.

Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node

Single-port and two-port SRAM designs in a 5-nm bulk FinFET node were tested for multi-cell upset (MCU) vulnerability against alpha particles, 14-MeV neutrons, thermal neutrons, and heavy ions with nominal and reduced supply voltages. Multi-cell upset contributions to single-event upset rates and observed bit-line upset ranges are presented for each particle as a function of supply voltage. Results show that MCUs account for a majority of events from high LET particles and neutrons at lower supply voltages. MCU shapes are shown for various sizes of upset clusters.

Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators

Image processing and machine learning applications benefit tremendously from hardware acceleration. Existing compilers target either FPGAs, which sacrifice power and performance for programmability, or ASICs, which become obsolete as applications change. Programmable domain-specific accelerators, such as coarse-grained reconfigurable arrays (CGRAs), have emerged as a promising middle-ground, but they have traditionally been difficult compiler targets since they use a different memory abstraction. In contrast to CPUs and GPUs, the memory hierarchies of domain-specific accelerators use push memories : memories that send input data streams to computation kernels or to higher or lower levels in the memory hierarchy and store the resulting output data streams. To address the compilation challenge caused by push memories, we propose that the representation of these memories in the compiler be altered to directly represent them by combining storage with address generation and control logic in a single structure—a unified buffer. The unified buffer abstraction enables the compiler to separate generic push memory optimizations from the mapping to specific memory implementations in the backend. This separation allows our compiler to map high-level Halide applications to different CGRA memory designs, including some with a ready-valid interface. The separation also opens the opportunity for optimizing push memory elements on reconfigurable arrays. Our optimized memory implementation, the Physical Unified Buffer, uses a wide-fetch, single-port SRAM macro with built-in address generation logic to implement a buffer with two read and two write ports. It is 18% smaller and consumes 31% less energy than a physical buffer implementation using a dual-port memory that only supports two ports. Finally, our system evaluation shows that enabling a compiler to support CGRAs leads to performance and energy benefits. Over a wide range of image processing and machine learning applications, our CGRA achieves 4.7× better runtime and 3.5× better energy-efficiency compared to an FPGA.

Design and implementation of Dual-Port Memory

Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or writes access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports.

Programmable FFT Processor using Dual RAM and ROM Technologies for Future 5G Communications

The high-throughput programmable Fast Fourier transform processor supports the usage of 2-stream 1024/2048/4096-point Fast Fourier Transforms and 1-to 4-stream 64/128-point Fast Fourier Transform for 4G,wireless local networks and for 5G.The proposed architecture which was designed is a well-intentionedfour-bank single-port SRAM which is being working in four-word data width, the design which is proposed gives us sixteen memory pathways . where the data is accessed up to this extent where it can be used in upcoming 5G. The radix-16 butterfly process element comprises of 2 cascaded parallel, pipelined radix-4 butterfly units which is specified. The projected memory-addressing methodology will effectively wear down single-port, merged-bank memory with high-radix process components. Comparing with typical memory based Fast Fourier Transform styles, the derived design has higher performance in expressions of area and power consumption. The architecture which is projected occupies the tiniest area of around1.21mm2.The processor supports 1966MS/s 4096-point FFT and frequency of 1GHz.The Electronic design automation synthesis results show the power consumption is 32.16mW.The SQNR performance analysis is 42.14 dB.

Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers

N×N filter operations are frequently used in various image processing algorithms in display driver circuits. The implementation of the N×N filter requires a storage element to temporarily retain N or N-1 lines of display data. The traditional approach for this temporary storage element for N×N image filter is either by using N blocks of memory to store N lines of display data with single-port six-transistor (6T) SRAM bit-cells or by using N-1 blocks of memory to store N-1 lines of display data with dual-port eight-transistor (8T) SRAM bit-cells. In this paper, a pseudo multi-port SRAM circuit is proposed for N×N filter in image processing in a display driver integrated circuit (IC). By using pre-read mechanism and word-line/column selection signal forwarding technique, the proposed approach only stores N-1 lines of display data and can use the small single-port 6T SRAM bit-cells. For a 3×3 filter application, the proposed approach reduces the overall layout area by 50.3% and 30.2% compared to the traditional dual-port 8T and single-port 6T memory implementations, respectively, in an industrial 0.18- μm CMOS technology. Furthermore, the power used to perform a 3×3 filter operation is reduced by 47% and 30.8% with the proposed approach as compared to the traditional dual-port 8T and signal-port 6T memory circuits, respectively, with slight degradation of the access speed.

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current

A Hardware Decoder Architecture for General String Matching Technique

This paper proposes a low cost hardware decoder design and architecture that supports general string matching (SM) using both a primary reference buffer (PRB) and a secondary reference buffer (SRB). An SM decoding module mainly performs string copy operation. The SM decoding module can also support intra block copy and palette decoding because both are actually two special cases of general string copy. The proposed architecture has four pipeline stages. The theoretical lowest system clock frequency required to guarantee worst case string copy operation using single-port SRAM is lower than the video output pixel rate, which is the product of frame resolution and frame rate. The design uses four pieces of SRAMs with size of 24K bytes, 16.5K bytes, 4K bytes, and 3K bytes, respectively. The first one is specific to SM and the other three are shared by traditional hybrid decoding operations. The SM decoding module has 69.5K logic gate count and can achieve 60 fps real time SM decoding for 4K ( $4096\times 2160$ ) video at 218 MHz working frequency.

A High-Throughput and Multi-Parallel VLSI Architecture for HEVC Deblocking Filter

This paper presents a high-throughput and multi-parallel VLSI hardware architecture for the deblocking filter in the HEVC video coding standard. First, an implementation-friendly and fast boundary judgment method is proposed to avoid using the original recursion loop approach. Then a dedicated parallel VLSI architecture composed of four parallel filtering cores is presented based on the proposed boundary judgment method. With the parallel luma/chroma filtering and parallel vertical/horizontal edges filtering order, the proposed VLSI architecture can process filtering operations for one largest coding unit (LCU) with less filtering cycles than other conventional approaches. Furthermore, filtering efficiency is improved due to a novel ping-pang buffer architecture and the on-chip single-port SRAM with dedicated data arrangement in the memory modules. Experimental results demonstrate that the proposed deblocking filter architecture improves the performance by 28–89% at the expense of the slightly increased gate count compared to the previously known architecture in HEVC. The proposed architecture can reach a high operating clock frequency of 278 MHz with TSMC 90 nm library and meet the real time requirement of the deblocking filter for 8 K × 4 K video format at 123 frame/s.

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

In the High Efficiency Video Coding (HEVC) standard, a notation of the transform unit (TU) is introduced with four different sizes, i.e., 4 $\times$ 4, 8 $\times$ 8, 16 $\times$ 16, and 32 $\times$ 32, which results in at least two problems in the use of discrete cosine transform/inversed discrete cosine transform (DCT/IDCT). One is changeable input/output format presented by DCT/IDCT when it deals with TUs of different sizes, which intensifies the nonconformity during the data exchange with other modules. The other is the demand for high throughput to traverse the vast possible TU partitions to find the best one, which would be easily dragged by an inefficient data exchange method. To solve this problem, a parallel-access data mapping method based on single-port static random access memory devices (SRAMs) is proposed in this brief. It can be applied to the data exchange buffers around DCT/IDCT in HEVC encoders to fulfill a high-throughput data exchange. Here, parallel access means one row of 1 $\times$ 32 pixels, two rows of 1 $\times$ 16 pixels, four rows of 1 $\times$ 8 pixels, or four rows of 1 $\times$ 4 pixels could be accessed in one cycle depending on the specific size of the current TU.

Multimode Memory-Based FFT Processor for Wireless Display FD-OCT Medical Systems

This paper presents a multimode memory-based Fast Fourier Transform (FFT) processor for a medical system aimed at Fourier-domain optical coherence tomography (FD-OCT) capable of supporting wireless displays based on multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM). The proposed FFT processor enables the use of 2-stream 4096/2048/1024-point FFTs and 1- to 4-stream 128/64-point FFTs for FD-OCT and OFDM applications, respectively. Using cost-effective four-bank single-port SRAM operating in four-word data width, the proposed design provides data access for up to sixteen memory paths. In conjunction with a proposed FFT kernel devised using hardware-efficient multiplication and cache units, the proposed system allows high-throughput multimode FFT operations in an energy- and area-efficient configuration. A test chip was designed using TSMC-0.18 μm CMOS technology with a core size of 4.8 mm 2 . Post-layout simulation performing 4096-point FFT at 80 MHz and the 128-point FFT at 40 MHz achieved throughput of 152 MS/s and 160 MS/s with power consumption of 156.2 mW and 69.9 mW, respectively. Compared to the previous approaches fully or partially supporting the specified OCT/OFDM FFTs, different degrees of area or energy efficiency improvements can be shown by our design depending on the FFT operation mode. In addition, system-level verification for practical OCT imaging was also performed using an FPGA platform.

Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT

This brief describes a new method to implement the single-port SRAM-based transpose memory for large size discrete cosine transform (DCT)/indiscrete cosine transform (IDCT) which are used in the latest video coding standard, such as high efficiency video coding. Instead of shift-register array or multiport SRAM, only single-port SRAM is used in the proposed design. A new diagonal data mapping scheme is proposed to reduce the number of SRAM banks used to implement the transpose memory. This design can be flexibly extended to support DCT/IDCT of different transform sizes and different data throughput rates. To support larger size DCT/IDCT, only the depth of SRAM needs to be increased. To support different data throughput rate, multiple SRAM banks are well organized according to the required throughput. Row access and column access can be perfectly supported under single port SRAM. The equivalent gate count per bit (EGC) of proposed approach is less than two, which is much more efficient than the previous method. It is suitable for real-time processing of the video with the resolution up to 1080P HD or even higher.

A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology

Sub-threshold leakage is a major issue for low power circuits design, especially for SRAM design in SoC. Sub-threshold leakage can be decreased by scaling down supply voltage. However, this may dramatically increase the circuit delay. In this paper, we propose a novel 6 T SRAM array structure with a switch module which operates in the near threshold region to reduce the leakage current. In order to verify our proposed leakage reduction scheme, we designed and simulated an 8192 kB SRAM array based on a 16 KB single port SRAM cell memory model in 55 nm process. Several 6 T SRAM Array instances are implemented in 55-nm 1P6M CMOS technology to measure the standby current of the proposed scheme as well. With the proposed technique, we achieved 28.3% reduction for leakage current compared to traditional 6 T SRAM array, in standby mode where gate leakage is dominant. The total penalty is 2% area increase and 1% speed reduction.

Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications

This paper presents a low-complexity multi-mode fast Fourier transform (FFT) processor for Digital Video Broadcasting-Terrestrial 2 (DVB-T2) systems. DVB-T2 operations need 1K/2K/4K/8K/16K/32K-point multiple mode FFT processors. The proposed architecture employs pipelined shared-memory architecture in which radix-2/22/23/24 FFT algorithms, multi-path delay commutator (MDC), and a novel data scaling approach are exploited. Based on this architecture, a novel low-cost data scaling unit is proposed to increase area efficiency, and an elaborate memory configuration scheme is designed to make single-port SRAM without degrading throughput rate. Also, new scheduling method of twiddle factor is proposed to reduce the area. The SQNR performance of 32K-point FFT mode is about 45.3dB at 11-bit internal word length for 256QAM modulation. The proposed FFT processor has a lower hardware complexity and memory size compared to conventional FFT processors.

48 Cycles-per-macro block deblocking filter accelerator for high-resolution H.264/AVC decoding

This study presents a high-throughput deblocking filter accelerator with 48 cycles-per-macro-block processing capability for H.264. This innovation is achieved by considering both luminance data and chrominance data at the same time in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously compute filtering of four edges. Besides, interleaved memory organisation is adopted to eliminate all the data conflicts. This design keeps the data scanning order compliant with that recommended for data communication between modules in H.264 systems. Hence, no interfacing overhead is required for reordering the input and output data. After being implemented by using a 0.18-µm CMOS technology, this work can achieve the real-time performance requirement of 6 K (6000×4000@30 fps) application when operated at 135 MHz frequency at a cost of 41.6 K gates along with 640 bytes single-port SRAM. Compared with previous works, the proposed design not only achieves higher real-time performance requirements but also possesses higher hardware computing efficiency.

A Programmable, Scalable-Throughput Interleaver

The interleaver stages of digital communication standards show a surprisingly large variation in throughput, state sizes, and permutation functions. Furthermore, data rates for 4G standards such as LTE-Advanced will exceed typical baseband clock frequencies of handheld devices. Multistream operation for Software Defined Radio and iterative decoding algorithms will call for ever higher interleave data rates. Our interleave machine is built around 8 single-port SRAM banks and can be programmed to generate up to 8 addresses every clock cycle. The scalable architecture combines SIMD and VLIW concepts with an efficient resolution of bank conflicts. A wide range of cellular, connectivity, and broadcast interleavers have been mapped on this machine, with throughputs up to more than 0.5 Gsymbol/second. Although it was designed for channel interleaving, the application domain of the interleaver extends also to Turbo interleaving. The presented configuration of the architecture is designed as a part of a programmable outer receiver on a prototype board. It offers (near) universal programmability to enable the implementation of new interleavers. The interleaver measures 2.09 m in 65 nm CMOS (including memories) and proves functional on silicon.

An 11 mm$^{2}$, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12$\ \mu$m CMOS

With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.12 mum CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.

Low-cost reconfigurable VLSI architecture for fast fourier transform

In this paper, a low-cost reconfigurable FFT processor employing novel dual-path pipelined sharedmemory architecture is presented. Based on this architecture, an elaborate memory configuration scheme is designed to make single-port SRAM available. Moreover, a mixed-radix butterfly unit is also designed, which makes the processor capable of multimode operation. Compared with previous ones, the proposed architecture can greatly reduce area. In addition, an optimized data scaling approach is proposed and the Signal-to-Quantization Noise Ratio (SQNR) of an 8Kpoint fixed-point FFT can achieve 52.7dB with the wordlength of 13bit. A test chip for DVB-T/H is implemented with the proposed architecture and fabricated in 0.18-μm single-poly six-metal CMOS process. The core area of this chip is 2.83mm2 with the power dissipation of 25.8mW at 20MHz.