A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology

Abstract

Sub-threshold leakage is a major issue for low power circuits design, especially for SRAM design in SoC. Sub-threshold leakage can be decreased by scaling down supply voltage. However, this may dramatically increase the circuit delay. In this paper, we propose a novel 6 T SRAM array structure with a switch module which operates in the near threshold region to reduce the leakage current. In order to verify our proposed leakage reduction scheme, we designed and simulated an 8192 kB SRAM array based on a 16 KB single port SRAM cell memory model in 55 nm process. Several 6 T SRAM Array instances are implemented in 55-nm 1P6M CMOS technology to measure the standby current of the proposed scheme as well. With the proposed technique, we achieved 28.3% reduction for leakage current compared to traditional 6 T SRAM array, in standby mode where gate leakage is dominant. The total penalty is 2% area increase and 1% speed reduction.