Single-phase Power Factor Correction Research Articles

Single-phase online interactive uninterruptible power supply design

The single-phase on-line interactive uninterruptible power supply (UPS) designed in this paper consists of three circuits, namely, a single-phase power factor correction circuit, a single-phase inverter circuit, and a bi-directional DC/DC circuit, each of which contains a main circuit as well as a control circuit. The principle, parameter design and control circuit design of each circuit are briefly described. The simulation model of the UPS is constructed, and the simulation results in normal and abnormal utility power are given to verify the correctness of the design.

Double-Loop Controller Design of a Single-Phase 3-Level Power Factor Correction Converter

This paper presents a study on the double-loop controller design technique for a single-phase power factor correction (PFC) three-level (TL) boost converter. Designing a double-loop controller using conventional methods is challenging due to the 120 Hz voltage ripple in the output voltage. This study proposes new double-loop control design methods using a band-stop filter and MATLAB SISOTOOL, detailed in a step-by-step sequence. A band-stop filter with a 120 Hz stop band is applied to the double-loop controller design. Modeling based on the state-space equation, applicable to the full duty range, is constructed to obtain the transfer function. The double-loop controller structure is then designed, and optimal gains that satisfy the design requirements are obtained through automatic tuning using the MATLAB SISOTOOL library. The simulation results demonstrate the performance of the proposed method, which is further verified by experimental results.

Third-Harmonic-Type Modulation Minimizing the DC-Link Energy Storage Requirement of Isolated Phase-Modular Three-Phase PFC Rectifier Systems

A three-phase ac/dc converter with high-frequency isolation can be realized as a monolithic three-phase or as a phase-modular system by combining three single-phase Power Factor Correction (PFC) rectifier modules with individual isolated dc-dc converters. Advantageously, for a phase-modular system the module configuration can be changed depending on the instantaneous input-output voltage ratio (i.e., a star-(Y)- or a delta-(Δ)-arrangement such that wide voltage ranges can be covered without a massive over-dimensioning of the main power components. However, the main disadvantage of a phase-modular converter realization is the fact that the input power of each PFC rectifier module pulsates at twice the mains frequency (which is inherent to single-phase power conversion) such that large dc-link capacitors are required. Recent literature predicts a substantial power pulsation reduction enabled by means of third-(3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> )-harmonic injection modulation which is applicable for the Y-connection (where a common-mode (CM) / zero-sequence (ZS) voltage is injected), and for the Δ-connection of the three single-phase PFC rectifier modules (where a CM / ZS current is injected). This changes the distribution of the power flow in the three-phase system and the power pulsation is shifted to higher frequencies. This paper experimentally verifies and extends the dc-link energy storage requirement reduction of the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation concept: In a first step, the derivation of the harmonic injection concept is recapitulated and suitable control methods are discussed for both CM voltage (Y-arrangement) and CM current (Δ-arrangement) injection. Further, an alternative CM voltage injection strategy with simplified reference generation based only on the instantaneous grid voltage measurements is presented and compared to the pure 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation. Measurement results obtained from a 6 kW prototype reveal a dc-link voltage variation and/or energy buffering reduction by up to 38.6 % enabled by the harmonic injection modulation compared to conventional operation without 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation.

DC-Link Capacitance Reduction in PFC Rectifiers Employing PI+Notch Voltage Controllers

It is well-known that adding a notch filter in series with the typically employed type-II (or PI) regulator allows improving the tradeoff between dc-link voltage dynamics and grid-side current total harmonic distortion (THD) in practical single-phase power factor correction rectifiers. The article demonstrates that notch filter utilization alternatively allows reducing the value of dc-link capacitance in case hold-up time requirement is absent. The revealed value of minimum capacitance is expressed by explicit function of possible mains frequency values range, maximum expected grid voltage magnitude, rated system power, dc-link voltage set point, maximum tolerable grid-side current THD, and the desired phase margin (PM) of dc-link voltage loop. It is demonstrated that the proposed approach yields fourfold reduction of dc-link capacitance for typical values of 5% tolerable grid-side current THD under 40° PM constraint. Experimental results exhibit close-fitting resemblance to corresponding analytical predictions, verifying the proposed methodology.

Single-Phase Hybrid Switched-Capacitor PFC Boost Rectifier With Low Voltage Gain

Power factor correction (PFC) rectifiers based on the classic boost topology have become widespread owing to their current input features, and can obtain optimal results in terms of power quality. However, several applications require an output dc voltage lower than the ac input voltage. In such cases, two-stage topologies provide lower voltage values at the output, which increases the number of components. Moreover, such topologies tend to incur higher losses and are costly. Therefore, a unidirectional hybrid single-stage single-phase PFC boost rectifier with a switched-capacitor cell and low voltage gain is proposed. Furthermore, the proposed topology has two active switches, and natural balance exists between the voltages of the capacitors. Therefore, an additional control system is not required. The proposed topology was theoretically analyzed and experimentally validated using a 1 kW prototype with two different operational situations: (A) 127 V ac and 100 Vdc; (B) 220 Vac and 200 Vdc, input and output voltages, respectively. The experimental results essentially reveal that the power factor is approximately one, and the total harmonic distortion of the input current is 4.6%. The maximum efficiency achieved was 96.5% in the operational situation (B).

Controlling Torque Ripple Vibration in a Single-Phase PFC Using the Neutral Point of an IPMSM

This paper proposes a method to reduce the torque ripple vibration of an integrated power factor correction (PFC) converter by using the zero-phase inductance of an interior permanent magnet synchronous motor (IPMSM) when the motor is not running. When an integrated PFC converter is applied to electric vehicle (EV) chargers, it is necessary to reduce the torque oscillation of the motor caused by the charging current. In an integrated PFC converter using an IPMSM, the zero-phase current and magnetomotive force harmonics of the permanent magnet cause torque vibration. In the proposed control method, the generated torque is estimated using the back EMF table, and the phase current is controlled to cancel it. The proposed method can be used to suppress torque vibration irrespective of the mechanical angle of the rotor. The effectiveness of the proposed method is experimentally verified. Using the proposed method, the torque vibration can be suppressed by up to 91.3% as compared to that in the case of the conventional control method. Furthermore, a power factor of 99.9% is achieved under a load condition of 1kW.

Design and Analysis of Zeta Converter for Power Factor Correction Using Cascade PSO-GSA-Tuned PI and Reduced-Order SMC

This paper presents the design and analysis of a single-phase power factor correction (PFC) scheme using a DC–DC Zeta converter operating in continuous conduction mode. The presented DC–DC converter exhibits non-linearity due to switching elements that degrades the performance of the converter. Therefore, this paper proposes a non-linear cascade control of particle swarm optimization-gravitational search algorithm (PSO-GSA) tuned proportional-integral (PI) and sliding mode controller (SMC) in outer and inner loop, respectively, to improve the performance of the converter. The robustness of the controller is analysed by applying the load and line variations to the converter. The simulation results showed that the steady state performance indices such as integral absolute error and integral square error, and transient performance indices like settling time and peak overshoot are significantly enhanced for the proposed cascade control scheme compared to the PSO and root locus method of tuning the outer PI with the inner SMC controller. The proposed control scheme gives better performance in terms of power factor improvement, percentage reduction in total harmonic distortion, and efficient tracking of output voltage for change in reference voltage compared to other techniques presented. Further, the performance of the proposed scheme is tested for battery charging application of the solar photovoltaic system. The demonstrated simulation results are validated by implementing the DC–DC Zeta converter in real-time hardware set-up.

A Six-Level Flying Capacitor Multilevel Converter for Single-Phase Buck-Type Power Factor Correction

This article investigates behavior of flying capacitor multilevel (FCML) converters in single-phase buck-type power factor correction (PFC) applications. Recent developments in FCML converters using gallium nitride (GaN) transistors are leveraged to improve power density of a single-phase 240 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{V}_{\text{RMS}}$</tex-math></inline-formula> ac to direct 48 V dc conversion stage in data center power delivery applications. Here, we experimentally demonstrate this concept in a digitally controlled six-level FCML converter hardware prototype. The experimental prototype can deliver 4.5 A average output current at 48 V, resulting in 216 W output power. A key contribution of this article is experimental demonstration of an FCML buck converter in a single-phase PFC application where the flying capacitor voltages follow fractions of the rectified input voltage by swinging at twice-line frequency.

Research on Cascaded Single Phase PFC Based on Predictive PI Control

In order to improve the charging speed and reduce the occupied volume of an electric vehicle charger, a single-phase boost power factor corrector (PFC) system with cascade CHB (cascaded H-bridge) topology was adopted. Due to the periodic fluctuation of single-phase AC input, there is a large double power frequency ripple component in the output voltage of an AC-DC converter. When capacitor voltage is used as output for feedback control, the control system has the characteristics of a non-minimum phase system. In light of these factors that affect the dynamic stability of the system, a control method is proposed to improve the dynamic characteristics of the system without affecting its steady-state performance. The predictive PI control strategy was adopted to predict the error input signal of the lag process to attenuate the jitter in the control system and improve the dynamic performance and anti-interference of the system. Finally, the feasibility of the scheme was verified by experiments.

Single-Phase PFC Rectifier With Integrated Flying Capacitor Power Pulsation Buffer

Single-phase Power Factor Correction (PFC) rectifiers with sinusoidal grid currents are inherently subject to an input power fluctuating at twice the mains frequency. In order to potentially mitigate bulky, heavy and failure-prone electrolytic dc-link capacitors, active Power Pulsation Buffer (PPB) concepts are proposed in the literature. For converter systems employing Flying Capacitor (FC) multilevel bridge-legs, the FCs can be utilized as a twice-mains frequency energy storage, i.e., as an integrated active PPB without the need for additional power components. Such ac-dc-stage-integrated FC PPBs capable of buffering the complete input power variation are known in literature which, however, require sophisticated control strategies with varying switching frequency and discontinuous conduction mode. This paper presents a novel ac-dc-stage-integrated FC-PPB approach which is compatible with standard PFC control concepts and enables a significant reduction in dc-link voltage variation. First, a control concept cycling the FC voltage in a wide range without interfering with the grid current controller is derived step by step and verified by means of circuit simulations. Design guidelines for the calculation of suitable FC capacitance values are presented and the limits in buffering capability are discussed. The concept is then experimentally verified with a 2.2kW three-level FC single-phase PFC rectifier employing 600V GaN power semiconductors where the dc-link voltage variation is reduced by 28% compared to conventional operation. Last, the applicability of the ac-dc-stage-integrated FC-PPB concept to other FC converter topologies is discussed.

Differential Mode Noise Prediction and Analysis in Single-Phase Boost PFC for the New Frequency Range of 9–150 kHz

High penetration of power electronics due to the concentration of switching frequency in the range of 9–150 kHz may create new challenging issues. Currently, regarding the recent version standard (IEC 61000-6-3), there is a lack of enough insight and fundamental studies despite reported electromagnetic interference (EMI) noise problems in this frequency range. Hence, this article proposes a time-frequency analytical modeling method for characterizing differential mode (DM) noise in a single-phase power factor correction (PFC) converter in this new frequency range. Provided comparative simulation analysis shows the proposed method's ability to estimate DM noise with a 9–150 kHz frequency range at high accuracy utilizing the double Fourier analysis method. Moreover, the obtained experimental results on a 1-kW single-phase boost PFC converter validate the proposed EMI modeling approach's effectiveness, demonstrating an error of less than 1.8 dB for the considered experimental case studies.

Review of the CM noise mitigation methods for the single-phase power factor correction converter

Several techniques to mitigate conducted electromagnetic interference (EMI) in single-phase power factor correction (PFC) converters have been reported in literatures. This paper mainly focuses on the review and classifications of the common-mode (CM) noise mitigation methods based on the novel structures, balance concept, novel modulation methods and so on. Through eliminating the noise generation or cut off the propagation path, those methods can mitigate the CM noise caused by the single-phase PFC converter. Besides, the comparisons and limitations are also discussed. It is believed that this review will be helpful to the design of the EMI filter for the switch-mode power system, which includes the PFC stages.

Second Harmonic Current Reduction Schemes for DC–DC Converter in Two-Stage PFC Converters

For the two-stage single-phase power factor correction (PFC) converter, its instantaneous input power pulsates at twice the line frequency, generating the second harmonic current (SHC) at the dc-bus port. The dc–dc stage is used to regulate the output voltage or the dc bus voltage in different applications, and the SHC reduction schemes for the dc–dc stage with different control objectives are discussed in this article. When the dc–dc stage regulates the output voltage, it is pointed out that the control bandwidth of the dc–dc stage is required to be high enough and the dc bus capacitor should be large enough to suppress the SHC, and the design of the dc bus capacitor is given. When the dc–dc stage regulates the dc bus voltage, a virtual impedance is added in series with the input/output of the dc–dc stage to suppress the SHC, and a virtual impedance is added in parallel with the dc bus to improve the dynamic performance. The selection and design of the virtual impedances are also given. Based on that, three specific control schemes are proposed for the dc–dc stage to suppress the SHC, and the parameters design method is also presented. Finally, a 3.3-kW two-stage single-phase PFC converter is fabricated and tested in the lab to verify the effectiveness of the proposed SHC reduction schemes.

Review of the CM noise mitigation methods for the single-phase power factor correction converter

Review of the CM noise mitigation methods for the single-phase power factor correction converter

Variable Output Voltage Switching Rectifier for Cathodic Protection Applications With DC–DC Variable Frequency and Duty-Cycle Full-Bridge Converter

Rectifiers used in cathodic protection (CP) applications convert ac voltage to variable dc output. This article proposes a switching converter for CP, mostly to enhance the efficiency in low to medium output powers, where the duty cycle is less than 30%. This device is composed of two parts, an ac-dc converter and a dc-dc full-bridge converter. The ac-dc converter is a single-phase boost-type power factor correction converter with emphasis on high efficiency, thus resulting in an almost unity power factor and fixed dc output voltage. The dc-dc full-bridge converter operates under pulsewidth modulation with the simultaneous change of frequency and duty-cycle (SCFD) control method responding to the user output power demand. The SCFD control strategy, in this converter, increases overall efficiency of the proposed rectifier. Finally, a 1875 W prototype is implemented and tested to verify the nearly fixed high efficiency for the converter in a wide operating range of the output power.

Hardware-in-the-Loop and Digital Control Techniques Applied to Single-Phase PFC Converters

Power electronic converters for power factor correction (PFC) play a key role in single-phase electrical power systems, ensuring that the line current waveform complies with the applicable standards and grid codes while regulating the DC voltage. Its verification implies significant complexity and cost, since it requires long simulations to verify its behavior, for around hundreds of milliseconds. The development and test of the controller include nominal, abnormal and fault conditions in which the equipment could be damaged. Hardware-in-the-loop (HIL) is a cost-effective technique that allows the power converter to be replaced by a real-time simulation model, avoiding building prototypes in the early stages for the development and validation of the controller. However, the performance-vs-cost trade-off associated with HIL techniques depends on the mathematical models used for replicating the power converter, the load and the electrical grid, as well as the hardware platform chosen to build it, e.g., microprocessor or FPGA, and the required number of channels and I/O types to test the system. This work reviews state-of-the-art HIL techniques and digital control techniques for single-phase PFC converters.

Capacitance Requirement Reduction in Single-Phase PFC With Adaptive Injection of Odd Harmonics

This article presents an adaptive harmonic injection approach for single-phase power factor correction (PFC) converters that reduce capacitance requirements and allow the use of smaller and more reliable film capacitors instead of electrolytic capacitors. Many applications require the converter’s rated power only during temporary intervals, whereas most of the time, the output power is much lower. In the proposed approach, the converter operates with a unity power factor below a given output power level. When the output power exceeds this value, then odd harmonics are linearly injected into the input current reference, up to the limits presented by IEC 61000-3-2. This approach reduces the voltage ripple across the power ripple buffering capacitor (PRBC), reducing the required capacitance value. The proposed approach is applied to the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula> -converter using enhanced automatic power decoupling (EAPD) control. The dynamic model to control PRBC average voltage is presented. A 1-kW prototype is built to validate the approach using a metalized polypropylene film capacitor as the PRBC. At full power, injecting third and fifth harmonics, the PRBC capacitance can be reduced from 22 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15~\mu \text {F}$ </tex-math></inline-formula> or 32%. It represents a further reduction in capacitance requirements for a converter that already requires low capacitance.

Simple current control without grid voltage sensor for traction solid-state transformer

This paper proposes a simple current control method without a grid voltage sensor for a rectifier of traction solid-state transformer. The proposed control scheme estimates the phase angle of grid voltage from the fundamental frequency current of the grid. The extracted phase signal is normalized to generate a sinusoidal current reference by adopting a scaling factor to achieve a unity gain. Since the proposed control method operates without the grid voltage sensor for power factor correction (PFC), it offers a cost-effective solution with a simple implementation structure. However, this method cannot guarantee its control performance under weak grid conditions, where the frequency of grid voltage often varies. Thus, the control parameters of the proposed method are discussed and analyzed to minimize performance degradation. To verify the feasibility of the proposed control method, simulations and experiments are carried out on a 2 kW single-phase PFC converter. The proposed method provides as much control performance as the conventional method, which uses the grid voltage sensor.

Stability Analysis of Two-Stage Single-Phase Converter System Adopting Electrolytic Capacitor-Less Second Harmonic Current Compensator

For the two-stage single-phase converter, including the power factor correction (PFC) ac-dc converter and dc-ac inverter, a second harmonic current compensator (SHCC) can be introduced to handle the second harmonic current (SHC) for removing the undesired electrolytic capacitor. Consequently, the two-stage single-phase converter becomes a multi-converter system. In this paper, the ac-dc stage or dc-ac stage in the system is categorized into two types in terms of the control objectives, i.e., the bus-voltage-controlled converter (BVCC) and the bus-current controlled converter (BCCC). The SHCC is a BCCC since its bus-port current is directly controlled, and the bus-port impedance of the SHCC is derived, which is affected by the ac-dc stage or dc-ac stage since the SHC reference is extracted from them. The system stability is investigated with the impedance-based stability criterion, and it is found that the system stability is different when the ac-dc stage or dc-ac stage is operated as a BVCC or a BCCC. Specifically, only when the ac-dc stage is operated as a BVCC, the system is unstable; while for other cases, the system is certainly stable. For the applications where the ac-dc stage is operated as a BVCC, a virtual resistor is introduced and realized by the control scheme of the SHCC to ensure the system stability. Finally, a two-stage single-phase PFC ac-dc converter is fabricated and tested to verify the theoretical analysis.

Average Periodic Delay-Based Frequency Adaptable Repetitive Control With a Fixed Sampling Rate and Memory of Single-Phase PFC Converters

This article proposes an average periodic delay-based repetitive controller for power factor correction (PFC) converters undergoing grid frequency variations. When the grid frequency is changed, a conventional repetitive controller requires an interpolation method or additional memory to achieve frequency adaptability. Furthermore, frequency adaptability can also be realized using a variable sampling frequency; however, this requires additional computation effort and a multirate digital control system. In this article, with a fixed sampling frequency and memory length, the proposed repetitive controller, which generates the average periodic delay unit, maintains its harmonic compensation performance under grid frequency variations. In the proposed method, the control variables are updated depending on the phase of the grid voltage to reflect the grid frequency deviations in the average period delay unit. Because no complicated software modification is necessary, the proposed scheme can be easily plugged in the existing control algorithm. The theoretical analysis and stability issues of the proposed scheme have been discussed in detail to ensure stable operation and disturbance rejection. Both the simulations and the experiments on a 1.5-kW PFC converter have been carried out to verify the effectiveness of the proposed repetitive control.