Single-loop Sigma-delta Modulator Research Articles

A Novel Approach for Realizing Loop-Filter in Low-Distortion Noise-Coupled ΣΔ Modulators

This paper presents an innovative general structure for a single-loop Sigma-Delta ([Formula: see text]) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure’s performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6[Formula: see text]dBFS and a sampling frequency of 2.56[Formula: see text]MHz, the signal to noise plus distortion (SNDR) was 81.9[Formula: see text]dB, and the dynamic range (DR) was 88[Formula: see text]dB for a 20[Formula: see text]KHz bandwidth. The modulator’s power consumption was 126.9[Formula: see text][Formula: see text]W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method.

A novel system-level modeling and design approach for high performance single-loop sigma-delta (∑Δ) modulators

PurposeThis paper attempted a novel approach for system-level modeling and simulation of sigma-delta modulator for low-frequency CMOS integrated analog to digital interfaces. Comparative analysis of various architectures topologies, circuit implementation techniques are described with analytical procedure for effective selection of topologies for targeted specifications.Design/methodology/approachVirtual instruments are presented in labview environment to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order. A fourth-order single-loop sigma-delta modulator is designed and verified in MATLAB simulink environment with careful selection of integrator weights to meet stable desired performance.FindingsThe proposed designed achieved SNDR of 122 dB and 20 bit resolution satisfying high-resolution requirements of low-frequency biomedical signal processing applications. Even though the simulation performed at behavioral level, the results obtained are considered as accurate, by including all non-ideal and non-linear circuit errors in simulation process.Originality/valueVirtual instruments using labview environment used to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order for accurate design.

Single-loop sigma delta modulator design and verification for cognitive IoT applications

PurposeA third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz.Design/methodology/approachThis paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications.FindingsThe proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping.Originality/valueThis paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.

A closed-loop ΣΔ modulator for micromechanical capacitive sensors

This paper describes a CMOS fully-differential switched-capacitor (SC) single-loop Sigma-Delta (ΣΔ) modulator specialized for highly precise micromechanical capacitive sensors. This design adopts a single-loop, fourth-order, one-bit quantization architecture with feedforward paths for lower nonlinearities and power consumption. Systematic optimization is used to avoid deterioration in conversion accuracy caused by capacitor mismatch. Chopper-stabilization and double-sampling techniques are also employed to enhance performances in noise depression. Manufactured in a standard 0.35 µm CMOS process, the ASIC occupies an area of 5.32 mm2 including 25 pads. This modulator achieves a signal-to-noise ratio (SNR) of 105.2 dB and dynamic range (DR) of 113.7 dB. The whole chip consumes 12.6 mW from a 5 V supply.

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18 μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16 (24) sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip—flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 kHz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma—delta modulator is applied. When its relative frequency resolution is settled to 10−6, the testing results show that the phase noises are −120.6 dBc/Hz at 1 MHz and −95.0 dBc/Hz at 100 kHz. The chip is 2.1 mm2 in UMC 0.18 μm CMOS. The power is 36 mW at a 1.8 V supply.

A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope

In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes overload.

A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.

Multi stage noise shaping sigma–delta modulator (MASH) for capacitive MEMS accelerometers

Electromechanical multi stage noise shaping (MASH) sigma–delta modulator (ΣΔM) has the advantages of inherent stability, high dynamic range, and high overload input level compared with the single loop sigma–delta-modulator approach. In this paper, a fourth order electromechanical MASH is studied by Simulink modelling and hardware implementation using surface mount PCB technology. The accelerometer used in the study is fabricated using a Silicon on Insulator (SOI) wafer with a device layer thickness of 50μm, using a dicing free and dry release process. The experimental results confirm the concept of the MASH structure and show its potential as a closed loop interface concept for a high performance capacitive MEMS accelerometer. The 4th order MASH electromechanical ΣΔM system improves the performance of the 2nd order electromechanical ΣΔM by 20dB, and shows a noise floor of −110dB. Furthermore, the system is capable of handling an acceleration input of up to ±1.5g. However, the MASH-ΣΔM is sensitive to the sensor and system parameters variation; it exhibited performance degradation of 10dB, due to a leakage of the quantization noise to the input signal.

A High Performance Fourth-Order Single-Loop Sigma Delta Modulator Applied in Micro-Inertial Sensors

This paper presents a fourth-order sigma delta (ΣΔ)modulator applied in micro-inertial sensors. After a introduction of sigma-delta modulator and its application in micro-inertial sensors, the system-level analysis and design is given and the gain coefficients is calculated. By the use of root locus, the stability of high order ΣΔ modulator is analyzed and it is got the minimum value of quantizer gain k is 0.287. The simulation shows that the signal to noise ratio (SNR) is 121.6 dB and the effective number of bits (ENOB) is 19.91 bits. When input level is smaller than -6 dBFs, the quantizer and integrators would not be overload and work well.

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer. This paper presents an improved 4th-order 1-bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion. The modulator was fabricated in a 0.35 μm CMOS process, and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply. The performance satisfies the requirements of a GSM system.

Low-power switched-capacitor delta—sigma modulator for EEG recording applications

This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram (EEG) monitoring applications. To reduce the power consumption, the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure. The modulator is designed in a 0.35-μm 2P4M standard CMOS process, with an active area of 365 × 290 μm2. Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 Hz signal bandwidth under a 64 over-sampling ratio. The whole circuit consumes 515 μW under a 2.5 V power supply, which is suitable for portable EEG monitoring.

Comparative study of multi stage noise shaping and single loop sigma–delta modulators for MEMS accelerometers

In this paper, two 4th order electromechanical sigma-delta modulators (∑ΔM) are compared at system level: a single-loop (SD4); and a multi-stage (MASH22) architecture. The comparison was performed for two different micromachined accelerometer sensing elements: one over-damped and the other under-damped; the control system with the latter requiring an electronic phase compensator for loop stability. The investigation shows that the 4th order MASH ∑ΔM is unconditionally stable and provides better noise shaping, higher signal-to-quantizationnoise-ratio (SQNR), higher dynamic range, and a higher overload input level compared with the SD4. The only drawback of the MASH22 is its sensitivity to component and parameter tolerances, which leads to a leakage of the quantization noise to the input signal and a degradation of the performance of the modulator.

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $\Delta \Sigma$ ADC in 90 nm CMOS

This paper describes the results of an implementation of a high speed DeltaSigma ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The DeltaSigma ADC is based on a switched-capacitor fourth-order single-loop DeltaSigma modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated DeltaSigma ADC and the digital signal processing block occupy 0.53 mm2 and 0.09 mm2, and consume 11.76 mW per channel.

Single-loop ΔΣ modulator with extended dynamic range

A single-loop delta–sigma modulator with extended dynamic range is proposed. It employs an auxiliary quantiser to process the quantisation error of the main quantiser. This simple addition guarantees improved stability over a wider signal input range and also reduces the sensitivity to the front-end DAC nonlinearity. Simulation results are provided to verify the effectiveness of this structure.

A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

A fully integrated CMOS frequency synthesizer for UHF RFID reader is implemented in a 0.18-mum CMOS technology. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer's phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. The modified transformer feedback voltage-controlled oscillator (VCO) exhibits enhanced tank impedance and even harmonic noise filtering to achieve low phase noise. A third-order 2-bit single-loop SigmaDelta modulator is optimized for the proposed synthesizer in terms of phase noise and power. The synthesizer provides a frequency resolution of 25-kHz with a tuning range from 1.03 GHz to 1.4 GHz . Phase noise of -70 dBc/Hz inband, -104 dBc/Hz at 200-kHz offset and - 121 dBc/Hz at 1-MHz offset with a reference spur of -84 dBc are measured at a center frequency of 1.17 GHz and a loop bandwidth of 35 kHz. Power dissipation is 4.92 mW from a 0.8 V supply.

Higher Order Noise-Shaping Filters for High-Performance Micromachined Accelerometers

Micromachined inertial sensors that have been incorporated in sigma-delta force-feedback loops have been proven to improve linearity, dynamic range, and bandwidth, and also provide a direct digital output. Previous work mainly focused on using the sensing element only to form a second-order single-loop sigma-delta modulator (SigmaDeltaM); however, the advantages of higher order single-loop electromechanical SigmaDeltaM have not been fully explored. High-performance inertial sensors require higher signal-to-quantization noise ratio (SQNR). This paper presents topologies for higher order single-loop electromechanical SigmaDeltaM with optimal stable coefficients that lead to a better SQNR. The topologies have good immunity to fabrication tolerances, which was verified by Monte Carlo analysis. The topologies are applicable not only to accelerometers but also to other inertial sensors such as gyroscopes.

Double-sampling single-loop /spl Sigma//spl Delta/ modulator topologies for broad-band applications

This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously reported techniques are used. The digital-to-analog converter's sampling paths are implemented with the single-capacitor approach and an additional zero is placed at the half of the sampling frequency of the modulator's noise transfer function (NTF). The detrimental effect of this additional zero on both the NTF and signal transfer function is also resolved through the proposed modulator architectures with a low additional circuit requirement.

A 900 mV 66 W Sigma-Delta Modulator Dedicated to Implantable Sensors

In this paper, a low-voltage low-power sigma-delta modulator dedicated to implantable sensing devices is presented. This second-order single-loop sigma-delta modulator is implemented with half-delay integrators. These integrators are based on new fully-differential CMOS class AB switched-Operational Transconductance Amplifier (switched-OTA). An on-chip voltage doubler is introduced to locally boost a supply voltage at the input stage of a conventional OTA in order to allow rail-to-rail signal swing. Experimental results of the modulator fabricated in CMOS 0.18 μm technology confirm its expected features of a peak signal-to-noise ratio (SNR) of 72 dB, a signal-to-noise distortion ratio (SNDR) of 62 dB in a 5 kHz signal bandwidth, and a power consumption lower than 66 μW with a 900 mV voltage supply.

FIR differentiators for quantized signals

The impact of quantization noise on a signal whose rate is to be estimated using a FIR differentiator is analyzed, concentrating on the important constant-rate case in order that the filter be optimized for systems with low-frequency rates of change. Formulae for the mean-squared error of the filter, the corresponding spectral characteristics, and general formulae governing the filter coefficients are derived. The characteristics of four specific differentiators, including a representative wideband differentiator, are examined and compared. It is shown that a differentiator that is in terms of its attenuation of white noise can also be considered with respect to quantization noise attenuation in certain circumstances. An elegant relationship is derived between worst-case RMS error and the fractional value of the rate at which this error occurs. Minimization of this worst-case mean-squared error is shown to be achieved with a simple differentiator. However, the corresponding average error is poor, and a simple nonlinear filter that minimizes the worst-ease error, while retaining a similar average mean-squared error to that of the optimum differentiator, is proposed. The equivalence between FIR differentiators and the decoders used in single-loop sigma-delta modulators is also highlighted.

Narrow-band variable center frequency single-loop and multistage sigma-delta modulators for bandpass signals

Oversampled narrow-band single-loop and multistage resonator-based bandpass sigma-delta (/spl Sigma/-/spl Delta/) modulators that can accommodate different passband center to sampling frequency ratios are reported. These tunable bandpass configurations are designed by analytically determining and subsequently verifying through detailed empirical simulations the required compensation hardware to deliver enhanced noise-shaping. It is demonstrated that comparatively superior in-band signal-to-noise ratios and dynamic ranges are attributed to the inclusion of appropriate digital feedforward and feedback compensators within these structures.