A 100 MS/s 4 MHz Bandwidth 70 dB SNR $\Delta \Sigma$ ADC in 90 nm CMOS

Abstract

This paper describes the results of an implementation of a high speed DeltaSigma ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The DeltaSigma ADC is based on a switched-capacitor fourth-order single-loop DeltaSigma modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated DeltaSigma ADC and the digital signal processing block occupy 0.53 mm2 and 0.09 mm2, and consume 11.76 mW per channel.