Single Integrated Circuit Research Articles

English

In electronics, adder is an obligatory component of every single integrated circuit. Adder is primary fast and secondly consumed less power and also chip area. We define various adders to perform addition method in VLSI technology. Full adder designing with respect to low power is becoming more popular now adays. It is an essential components of every ALU block. To perform fast arithmetic operations, ripple carry adder is one of the fastest adders used in many data- processing processors. In this paper we analysed a full adder circuit in different sub-micron technologies and obtain low power and minimum delay of it. We also design area efficient layout of full adder schematic. With the help of full adder low power with delay consumed model we design a ripple carry adder schematic and make an area efficient layout of it[1].

Low-jitter wide-range integrated time interval/delay generator based on combination of period counting and capacitor charging.

We present the design, operation, and test results of a new time interval/delay generator that provides the resolution of 0.3 ps, jitter below 10 ps (rms), and wide delay range of 10 s. The wide range has been achieved by counting periods of a reference clock while the high resolution and low jitter have been obtained through the two-time use of inner interpolation. This interpolation, based on charging of a single capacitor, provides both the precise external trigger synchronization and accurate generation of residual time interval. A combination of both processes virtually eliminates triggering indeterminacy. The jitter between the trigger and output is below 1 ps, which ensures a high performance delay. The generator is integrated in a single application specific integrated circuit chip using a standard cost-effective 0.35 μm CMOS process.

Noise and Sensitivity Improvement using SC Filters

The discrete time switched capacitor (SC) based filters have number of advantages over the classical continuous time active RC based filters, the one most important being reduced circuit silicon area, allowing SC filters to be integrated to a single monolithic integrated circuit (IC). In this paper we have designed fifth order Chebyshev low pass SC filter, with a cut-off frequency fc = 3.4 kHz, and pass-band ripple αmax = -0.5 dB, and we have compared its time and frequency performance with a performance of the active RC based filter. The both SC and active RC filters are realized as a cascade of two second order sections and one first order section. All filter analysis has been performed using MATLAB and SPICE program packages where SC based filter has shown significant noise and sensitivity improvement, when compared with active RC based filter.

Implementation of Switching System for High Speed Data Transmission using VHDL

Switching system is used for data transmission between two communicating Channels. This transmission can be done via trunks or it can be fully wireless, technically termed as Telephone Switching and Mobile switching, respectively. The implementation of the switching system using VHSIC hardware description language is more reliable and efficient than the previous switching system (1). It converts entire bulky switching unit which consists of routers, multiplexers, decoders, counters in to a single integrated circuit . Simulation results are presented for transfer of data from input subscriber to the output subscriber using sequential write / random read mode with the timing diagram(2). To verify the transfer of data from input subscriber to the output subscriber a 32 bit op-code is assumed in which each bit represents a specific function. In our Paper we have worked on Switching System for two different channels using VHDL, each channel have 16 users. They can communicate either intra channel or inter channel. We are also providing Caller ID facility. The incoming data through the inlets are written into the data memory and later read out to the appropriate outlets. The incoming and outgoing data are usually in serial form whereas the data are written into and read out of the memory in parallel form. That's why it is necessary to perform serial to parallel conversion and parallel to serial conversion at the inlets and outlets respectively. We have selected 32 bit op-code for communication among these channels because its ability to define all the functions. This 32 bit op-code is responsible for caller id and transmission and reception of particular data. I have implemented my work with the help of Xilinx ISE and Modelsim 10.2a.

Application Workload Modelling via Run-Time Performance Statistics

Modern mobile nomadic devices for example internet tablets and high end mobile phones support diverse distributed and stand-alone applications that were supported by single devices a decade back. Furthermore the complex heterogeneous platforms supporting these applications contain multi-core processors, hardware accelerators and IP cores and all these components can possibly be integrated into a single integrated circuit (chip). The high complexity of both the platform and the applications makes the design space very complex due to the availability of several alternatives. Therefore the system designer must be able to quickly evaluate the performance of different application architectures and implementations on potential platforms. The most popular technique employed nowadays is termed as system-level-performance evaluation which uses abstract workload and platform capacity models. The platform capacity models and application workload models reside at a higher abstraction-level. The platform and application workload models can be instantiated with reduced modeling effort and also operate at a higher simulation speed. This article presents a novel run-time statistics based application workload model extraction and platform configuration technique. This technique is called platform COnfiguration and woRkload generatIoN via code instrumeNtation and performAnce counters (CORINNA) which offers several advantages over compiler based technique called ABSINTH, and also provides automatic configuration of the platform processor models for example cache-hits and misses obtained during the application execution.

Ultralocalized thermal reactions in subnanoliter droplets-in-air

Miniaturized laboratory-on-chip systems promise rapid, sensitive, and multiplexed detection of biological samples for medical diagnostics, drug discovery, and high-throughput screening. Within miniaturized laboratory-on-chips, static and dynamic droplets of fluids in different immiscible media have been used as individual vessels to perform biochemical reactions and confine the products. Approaches to perform localized heating of these individual subnanoliter droplets can allow for new applications that require parallel, time-, and space-multiplex reactions on a single integrated circuit. Our method positions droplets on an array of individual silicon microwave heaters on chip to precisely control the temperature of droplets-in-air, allowing us to perform biochemical reactions, including DNA melting and detection of single base mismatches. We also demonstrate that ssDNA probe molecules can be placed on heaters in solution, dried, and then rehydrated by ssDNA target molecules in droplets for hybridization and detection. This platform enables many applications in droplets including hybridization of low copy number DNA molecules, lysing of single cells, interrogation of ligand-receptor interactions, and rapid temperature cycling for amplification of DNA molecules.

Other people's knowledge [Reflections

I was visiting a high-tech company whose principal business was advanced chip design. A young engineer showed me his latest prototype. It was a circuit board dominated by a single large integrated circuit. It contained, he told me, more than 2 billion transistors. I'd never done anything remotely similar myself, and I wondered how I'd feel as a new engineer in some company being given a "Mission: Impossible" assignment like that. "How can you possibly design something so complex?" I asked. The young engineer just shrugged his shoulders. No big deal, he appeared to be saying. After a little further prodding, he confessed that, after all, there was a large collection of previously designed cells, and the computer design tools were pretty awesome. Not much to it, really. Technology has gotten exponentially more complex with the passing years, and yet engineers are turned out of universities in the same four-year cycle that they used decades ago. How is this possible?

A new electronic assay enables ultrasensitive detection of diverse biological analytes—nucleic acids, proteins and small molecules—on a single integrated circuit

Abstract

A Glimpse of the Future

The RF and microwave world has largely been exempt from the rigors of Moore's law, whereas aggressive scaling in the digital world has been the norm for several decades. But now, as CMOS transistors have picosecond switching speeds and transition frequencies in the tens to 100s of GHz, there is an opportunity for the integration of RF and microwave components into a complete system on a single integrated circuit (IC). Single-chip transceivers for wireless local area network (LAN) and femtocell base stations are already a commercial reality. As with complex digital systems, the demand for first-pass design success requires that accurate predictive models are available for the subsystem components of the whole system, enabling the system design to be simulated and any errors or faults remedied before the design is committed to hardware. This will save time and the cost of unnecessary fabrication and test of the complete system.

Integration of 1.3-$\mu{\rm m}$ Quantum-Dot Lasers With ${\rm Si}_{3}{\rm N}_{4}$ Waveguides for Single Mode Optical Interconnects

A single mode photonic integrated circuit, consisting of a monolithically integrated quantum-dot laser and a suitably designed <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Si}_{3}{\rm N}_{4}$</tex></formula> waveguide, is demonstrated. The 1.3- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> quantum-dot laser incorporates a superlattice barrier, p-doping, and tunnel injection in the active region, demonstrating operation up to 85 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}{\rm C}$</tex></formula> with excellent temperature stability (high <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm T}_{0}$</tex></formula> ). The two devices are optimally groove coupled to minimize the losses. Integration of the tapered waveguide with a quantum-dot cross laser is also demonstrated.

A High Resolution Vernier Ring Oscillator with Ultra-Low Temperature Drift

Nowadays, the precise measurement of the time interval between two events with very fine timing resolution is common challenge in the test and measurement instrumentation. This paper present a new high resolution vernier ring oscillator(VRO), which can measures the clock jitter as the operation temperature rises.The goal of this work focuses on the design of a TDC of temperature stable oscillator and we propose an ultra-low temperature drift of a differential delay cell oscillator based on a proportional to absolute temperature(PTAT) compensation methodology. It is very desirable to have a single integrated circuit producing a stable high resolution timing circuit over a wide temperature range developed in a standard CMOS process. By the simple concept of vernier delay line and two ring oscillators, the proposed can achieve a fine time resolution with wide working temperature. For each channel of ring oscillator, the relative delay time is fine tuned by an external VBIAS input. From 25°Cto 45°C, the maximum error percent of delay time without compensation circuits is more than 2.9%, but it with compensation circuits is less than 0.3%. The different operating temperature will affect entire circuit and the delay time of ring oscillator. A compensation circuit to reduce the variety of ring oscillator is also added. The new architecture of high resolution TDC with temperature compensated circuit is proven to be applicable in high precision clock applications which is analyzed and implemented in a CMOS 0.18μm 1P6M process.

Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package

The current study investigates the effects of increasing the number of stacking chips and applying three types of inlet positions to the void formation in three-dimensional (3D) stacked flip-chip packaging. A scaled-up single integrated circuit packaging was performed, and the mechanism of void formation was studied throughout the experiment. The entrapment of air was visualized clearly in the experiment because of the unstable flow front during encapsulation. In the 3D stacked flip-chip packaging, the Castro–Macosko model with curing effect was written into user-defined functions and incorporated into the FLUENT software to describe the behavior of the molding compound. The increase in the number of stacking flip-chips increased the void in the package, which tended to form at the stacking chips region. Moreover, the application of three different inlet positions, namely, typical, diagonal, and top center inlets, significantly influenced the flow mechanism and void concentration. Knit lines were identified at the interface between the flows that occurred in the encapsulation. The current modeling also predicted the conversion of the compound. The simulation and experimental results were validated, thus proving that the current virtual modeling could handle the problems during encapsulation excellently.

Integrated phased‐array switches for large‐scale photonic routing on chip

AbstractIntegrated phased‐array optical switches, having a high port‐count scalability and broad spectral coverage, can potentially be used as building blocks of large‐scale optical routers. In this article, recent works on monolithically integrated InP phased‐array switches and their applications to optical packet switching (OPS) are reviewed. After describing the theory of integrated phased‐array switches, experimental results on a single‐stage 1 × 16 switch, which features wavelength‐independent nanosecond switching characteristics, are presented. A series of OPS experiments, employing high‐bit‐rate optical packets with different modulation formats and a tunable optical buffering experiment are presented as potential applications of these switches. Finally, a large‐scale monolithic switch with as many as 100 ports is realized on a single photonic integrated circuit by cascading the phased‐array switches.

Design of a Sensor Coil and Measurement Electronics for Magnetic Induction Tomography

Magnetic induction tomography (MIT) is a tomographic imaging technique that is able to map the electromagnetic properties within an object or vessel from magnetic field measurements. Excitation coils are used to induce eddy currents in the medium, and the magnetic field produced by the induced eddy current is then sensed by receiver coils. Because of its noncontact nature, MIT is particularly attractive for biomedical and some industrial applications, such as pipe-flow monitoring, when compared with traditional contact electrode-based electrical impedance tomography. This paper describes the design and performance of an MIT transceiver circuit that can operate from 400 kHz to 12 MHz. The in-phase and quadrature (I/Q) demodulation technique is used to measure the signal perturbation due to the induced conduction eddy currents. The transceiver circuit design employs a single integrated circuit, containing a variable-gain amplifier and an I/Q demodulator. This paper contains characterizations of the transceiver's measurement noise, system stability, and sensitivity for detecting saline solutions and metal plates. A novel balanced coaxial screened coil structure with integrated current sensing was also developed to minimize capacitive coupling between coils and to allow measurement of the current in the driving coils. Experiments were carried out at 3 and 10 MHz using bottles of saline solutions (1%-5% concentration) and metal sheets (aluminum and steel) to verify the sensitivity for conductivity imaging.

Glass and Quartz Microscintillators for CMOS-Compatible Multispecies Radiation Detection

This paper reports on a small-scale radiation detector that is sensitive to alpha, beta, gamma, and neutron radiation using scintillators doped with boron nanoparticles utilizing CMOS fabrication techniques. Two types of microscintillators have been fabricated and tested: One relies on sintered glass frit doped with boron nanoparticles, and the other uses quartz with boron diffused into the substrate. Radiation impinging on the scintillation matrix produces varying optical pulses of varying intensities depending on the type of radiation particle. The optical pulses are differentiated by on-chip pulse height spectroscopy and recorded on a microcontroller. The pulse height circuitry has been fabricated with both discrete circuits and designed into a single integrated circuit package. The quartz substrates have shown to be more transparent to the wavelength of the created optical pulses, which results in a higher count rate when compared to the tested glass scintillator. The quartz scintillator also shows better absorption of radiation particles, resulting in better detection efficiencies than the glass. The quartz also has been tested with varying doping levels and has the ability to detect neutrons. Source differentiation between 137Cs and 60Co has also been demonstrated.

English

In the global IC industry, business models have evolved into design foundry models and manufacturing foundry service models over the past twenty years. The concept of system-on-a-chip (SoC) refers to integrating all components of a computer or other electronic system in a single integrated circuit (IC). Due to the increasing complexities of SoC devices, it is impossible for one IC design house to have the state-of-the-art expertise required to make all the hardware and software components required for an SoC. Based on SoC needs for intellectual property (IP) reuse and design reuse, this study analyzes a new open business model, called design foundry. Design houses must use a design foundry, an innovation intermediary, to combine their internally generated IPs with IPs acquired externally. This paper uses the SoC design foundry as a case to examine the evolution, SoC problems, and the core value of innovation intermediaries in the whole IC industry. Further, it demonstrates how design foundries create ecological benefits by teaming up with suppliers and customers in the IC industry. This research is the first known study to explore the emerging service gaps, value creation, and value capture processes created by an SoC design foundry. &nbsp; Key words:&nbsp;Open business models, open innovation, design foundry, innovation intermediary, system-on-a-chip (SoC), integrated circuit (IC) Industry.

Beam steering array antenna controlled by optical wavelength

We developed a beam forming network (BFN) for an array antenna with 5 elements radiating 3 independently steerable beams, and measured the phase shift characteristics. The main part of the BFN is integrated as a single photonic integrated circuit (PIC) chip using birefringent Lithium Niobate (LN) waveguide. The phase distribution among the 5 element antennas is controlled by the wavelength tuning of an optical RF source. Highly linear phase shift characteristics with the sensitivity of 8.24°/nm are achieved. By using 3 tunable optical RF sources allocated to different wavelength range, the PIC chip can generate feeding signals for 3 independently steerable beams.

Real-time full-field arbitrary optical waveform measurement

The development of a real-time optical waveform measurement technique with quantum-limited sensitivity, unlimited record lengths and an instantaneous bandwidth scalable to terahertz frequencies would be beneficial in the investigation of many ultrafast optical phenomena. Currently, full-field (amplitude and phase) optical measurements with a bandwidth greater than 100 GHz require repetitive signals to facilitate equivalent-time sampling methods or are single-shot in nature with limited time records. Here, we demonstrate a bandwidth- and time-record scalable measurement that performs parallel coherent detection on spectral slices of arbitrary optical waveforms in the 1.55 µm telecommunications band. External balanced photodetection and high-speed digitizers record the in-phase and quadrature-phase components of each demodulated spectral slice, and digital signal processing reconstructs the signal waveform. The approach is passive, extendable to other regions of the optical spectrum, and can be implemented as a single silicon photonic integrated circuit. A measurement scheme that is capable of recording the amplitude and phase of arbitrary shaped optical waveforms with a bandwidth of up to 160 GHz is presented. The approach is compatible with integration on a silicon photonic chip and could aid the study of transient ultrafast phenomena.

On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques

With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from [18], [19], and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in [19]. The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.

Characterization of new materials for capacitor formation in integrated circuit technology

There have been tremendous developments in electronic technology in the last 40 years as evidenced by the widespread availability of computers, mobile phones and electronic entertainment systems and their continued shrinking in size and cost. Much of the improvement in the performance of electronic systems can be traced to developments in Integrated Circuits (ICs) (“microchips”) which form the fundamental building blocks of modern electronics technology. Within an IC, the most important electronic component is the transistor and it is the transistor that is used to implement the operations associated with computer logic. With each generation of technology, the size of the transistors is reduced and more of them can fit on a single IC, which allows more powerful devices to be made that take up the same or even smaller space and draw less power from the battery. This trend regarding the scaling down in size of the transistors was ...