Abstract
In electronics, adder is an obligatory component of every single integrated circuit. Adder is primary fast and secondly consumed less power and also chip area. We define various adders to perform addition method in VLSI technology. Full adder designing with respect to low power is becoming more popular now adays. It is an essential components of every ALU block. To perform fast arithmetic operations, ripple carry adder is one of the fastest adders used in many data- processing processors. In this paper we analysed a full adder circuit in different sub-micron technologies and obtain low power and minimum delay of it. We also design area efficient layout of full adder schematic. With the help of full adder low power with delay consumed model we design a ripple carry adder schematic and make an area efficient layout of it[1].
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Innovative Research in Computer and Communication Engineering
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
