Parallel Single Instruction Multiple Data Research Articles

The updates in Libcint 6: More integrals, API refinements, and SIMD optimization techniques.

Libcint is a library designed for the evaluation of analytical integrals for Gaussian type orbitals. It prioritizes simplicity, ease of use, and efficiency for the development of quantum chemistry programs. In the release of version 6.0, Libcint supports the computation of integrals for various operators, such as overlap, Coulomb, Gaunt, Breit, attenuated Coulomb, Slater-type geminals, and Yukawa potential, as well as arbitrary orders of derivatives for these operators. To enhance the usability of the library, Libcint provides a uniform function signature for all integral functions. A code generator is included to automate the implementation of new integrals. To achieve better performance on modern central processing unit architectures, the library employs explicit single instruction multiple data parallelization in the code implementation.

Accelerating minimap2 for long-read sequencing applications on modern CPUs.

Long-read sequencing is now routinely used at scale for genomics and transcriptomics applications. Mapping long reads or a draft genome assembly to a reference sequence is often one of the most time-consuming steps in these applications. Here we present techniques to accelerate minimap2, a widely used software for this task. We present multiple optimizations using single-instruction multiple-data parallelization, efficient cache utilization and a learned index data structure to accelerate the three main computational modules of minimap2: seeding, chaining and pairwise sequence alignment. These optimizations result in an up to 1.8-fold reduction of end-to-end mapping time of minimap2 while maintaining identical output.

Acceleration of object tracking in high‐speed videogrammetry using a parallel OpenMP and SIMD strategy

AbstractHigh‐speed cameras are able to effectively and efficiently obtain the location of moving objects over time in many practical applications. In order to meet the requirement for fast computing and processing in the object‐tracking process, this paper adopts parallel computing to process multiple video‐image sequences by using open multi‐processing (OpenMP) and single‐instruction multiple data (SIMD) simultaneously, combined with a coarse‐to‐fine matching method. Experimental results showed that the proposed method: (1) has a high accuracy compared with other methods; (2) demonstrates a higher computational efficiency than other methods; and (3) has an efficiency running on a laptop equivalent to other methods running on a computer workstation.

AUKE

Focal-plane Sensor-Processor Arrays (FPSPs) are new imaging devices with parallel Single Instruction Multiple Data (SIMD) computational capabilities built into every pixel. Compared to traditional imaging devices, FPSPs allow for massive pixel-parallel execution of image processing algorithms. This enables the application of certain algorithms at extreme frame rates (>10,000 frames per second). By performing some early-stage processing in-situ, systems incorporating FPSPs can consume less power compared to conventional approaches using standard digital cameras. In this article, we explore code generation for an FPSP whose 256 × 256 processors operate on analogue signal data, leading to further opportunities for power reduction—and additional code synthesis challenges. While rudimentary image processing algorithms have been demonstrated on FPSPs before, progress with higher-level computer vision algorithms has been sparse due to the unique architecture and limits of the devices. This article presents a code generator for convolution filters for the SCAMP-5 FPSP, with applications in many high-level tasks such as convolutional neural networks, pose estimation, and so on. The SCAMP-5 FPSP has no effective multiply operator. Convolutions have to be implemented through sequences of more primitive operations such as additions, subtractions, and multiplications/divisions by two. We present a code generation algorithm to optimise convolutions by identifying common factors in the different weights and by determining an optimised pattern of pixel-to-pixel data movements to exploit them. We present evaluation in terms of both speed and energy consumption for a suite of well-known convolution filters. Furthermore, an application of the method is shown by the implementation of a Viola-Jones face detection algorithm.

Accelerating finite-rate chemical kinetics with coprocessors: Comparing vectorization methods on GPUs, MICs, and CPUs

Accurate and efficient methods for solving stiff ordinary differential equations (ODEs) are a critical component of turbulent combustion simulations with finite-rate chemistry. The ODEs governing the chemical kinetics at each mesh point are decoupled by operator-splitting allowing each to be solved concurrently. An efficient ODE solver must then take into account the available thread and instruction-level parallelism of the underlying hardware, especially on many-core coprocessors, as well as the numerical efficiency. A stiff Rosenbrock and a nonstiff Runge–Kutta ODE solver are both implemented using the single instruction, multiple thread (SIMT) and single instruction, multiple data (SIMD) paradigms within OpenCL. Both methods solve multiple ODEs concurrently within the same instruction stream. The performance of these parallel implementations was measured on three chemical kinetic models of increasing size across several multicore and many-core platforms. Two separate benchmarks were conducted to clearly determine any performance advantage offered by either method. The first benchmark measured the run-time of evaluating the right-hand-side source terms in parallel and the second benchmark integrated a series of constant-pressure, homogeneous reactors using the Rosenbrock and Runge–Kutta solvers. The right-hand-side evaluations with SIMD parallelism on the host multicore Xeon CPU and many-core Xeon Phi co-processor performed approximately three times faster than the baseline multithreaded C++ code. The SIMT parallel model on the host and Phi was 13%–35% slower than the baseline while the SIMT model on the NVIDIA Kepler GPU provided approximately the same performance as the SIMD model on the Phi. The runtimes for both ODE solvers decreased significantly with the SIMD implementations on the host CPU (2.5–2.7×) and Xeon Phi coprocessor (4.7–4.9×) compared to the baseline parallel code. The SIMT implementations on the GPU ran 1.5–1.6 times faster than the baseline multithreaded CPU code; however, this was significantly slower than the SIMD versions on the host CPU or the Xeon Phi. The performance difference between the three platforms was attributed to thread divergence caused by the adaptive step-sizes within the ODE integrators. Analysis showed that the wider vector width of the GPU incurs a higher level of divergence than the narrower Sandy Bridge or Xeon Phi. The significant performance improvement provided by the SIMD parallel strategy motivates further research into more ODE solver methods that are both SIMD-friendly and computationally efficient.

GPUSGD: A GPU‐accelerated stochastic gradient descent algorithm for matrix factorization

SummaryMatrix factorization is one of the leading techniques for many applications such as social network‐based recommendation systems. As of today, many parallel stochastic gradient descent (SGD) methods have been proposed to address the matrix factorization issue on shared‐memory (multi‐core) systems and distributed systems. However, these methods cannot be improved significantly on graphics processing unit (GPU) because the serious over‐writing problem and thread divergence may occur. The fundamental reason for such undesired results is that GPU is a parallel single instruction multiple data device, which only can greatly improve the applications with fine‐grained parallelism. In this paper, we propose an efficient GPU algorithm, named GPUSGD, to solve the matrix factorization problem based on SGD method. The major advantage of the proposed GPUSGD is that such method not only can handle the over‐writing problem but also can avoid the performance loss caused by the thread divergence. The experimental results show that GPUSGD performs much better in accelerating the matrix factorization compared with the existing state‐of‐the‐art parallel methods. To the best of our knowledge, this is the first work that develops a parallel SGD method to improve the matrix factorization on GPU. Copyright © 2015 John Wiley & Sons, Ltd.

FPGA-based many-core System-on-Chip design

Massively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data (SIMD) many-core architectures have been adopted for multimedia and signal processing applications with massive amounts of data parallelism where both performance and flexible programmability are important metrics. However, this class of processors has faced many challenges due to its increasing fabrication cost and design complexity. Moreover, the increasing gap between design productivity and chip complexity requires new design methods. Nowadays, the recent evolution of silicon integration technology, on the one hand, and the wide usage of reusable Intellectual Property (IP) cores and FPGAs (Field Programmable Gate Arrays), on the other hand, are attractive solutions to meet these challenges and reduce the time-to-market. The objective of this work is to study the performances of massively parallel SIMD on-chip architectures with current design methodologies based on recent integration technologies. Flexibility offered by these new design tools allows design space exploration to search for the most effective implementations. This work introduces an IP-based design methodology for easy building configurable and flexible massively parallel SIMD processing on FPGA platforms. The proposed approach allows implementing a generic parallel architecture based on IP assembly that can be tailored in order to better satisfy the requirements of highly-demanding applications. The experimental results show effectiveness of the design methodology as well as the performances of the implemented SoC.

SIMD parallel MCMC sampling with applications for big-data Bayesian analytics

Computational intensity and sequential nature of estimation techniques for Bayesian methods in statistics and machine learning, combined with their increasing applications for big data analytics, necessitate both the identification of potential opportunities to parallelize techniques such as Monte Carlo Markov Chain (MCMC) sampling, and the development of general strategies for mapping such parallel algorithms to modern CPUs in order to elicit the performance up the compute-based and/or memory-based hardware limits. Two opportunities for Single-Instruction Multiple-Data (SIMD) parallelization of MCMC sampling for probabilistic graphical models are presented. In exchangeable models with many observations such as Bayesian Generalized Linear Models (GLMs), child-node contributions to the conditional posterior of each node can be calculated concurrently. In undirected graphs with discrete-value nodes, concurrent sampling of conditionally-independent nodes can be transformed into a SIMD form. High-performance libraries with multi-threading and vectorization capabilities can be readily applied to such SIMD opportunities to gain decent speedup, while a series of high-level source-code and runtime modifications provide further performance boost by reducing parallelization overhead and increasing data locality for Non-Uniform Memory Access architectures. For big-data Bayesian GLM graphs, the end-result is a routine for evaluating the conditional posterior and its gradient vector that is 5 times faster than a naive implementation using (built-in) multi-threaded Intel MKL BLAS, and reaches within the striking distance of the memory-bandwidth-induced hardware limit. Using multi-threading for cache-friendly, fine-grained parallelization can outperform coarse-grained alternatives which are often less cache-friendly, a likely scenario in modern predictive analytics workflow such as Hierarchical Bayesian GLM, variable selection, and ensemble regression and classification. The proposed optimization strategies improve the scaling of performance with number of cores and width of vector units (applicable to many-core SIMD processors such as Intel Xeon Phi and Graphic Processing Units), resulting in cost-effectiveness, energy efficiency (‘green computing’), and higher speed on multi-core x86 processors.

Legendre moments as high performance bone biomarkers: computational methods and GPU acceleration

We investigate the use of Legendre moments as biomarkers for an efficient and accurate classification of bone tissue on images coming from stem cell regeneration studies. Legendre moments are analysed from three different perspectives: (1) their discriminant properties in a wide set of preselected vectors of features based on our clinical and computational experience, providing solutions whose accuracy exceeds 90%; (2) the amount of information to be retained when using principal component analysis to reduce the dimensionality of the problem to either 2, 3, 4, 5 or 6 dimensions and (3) the use of the -k-feature set problem to identify a k = 4 number of features which are more relevant to our analysis from a combinatorial optimisation approach. These techniques are compared in terms of computational complexity and classification accuracy to assess the strengths and limitations of the use of Legendre moments. The second contribution of this work goes to reduce the computational complexity by using graphics processing units (GPUs) and compute unified device architecture programming [Nvidia Developer Zone. 2014. CUDA. Available from: http:developer.nvidia.comobjectcuda.html]. We exploit single instruction multiple data parallelism and memory bandwidth on GPUs to accelerate the process to more than a 5 × factor on each 64 × 64 image tile. The result is a powerful combination of software and hardware methods which deliver a much faster response in contrast with existing solutions coming from conventional programming on multicore CPU platforms, thus offering a high performance alternative in clinical practice for real-time imaging.

Implementation of fast HEVC encoder based on SIMD and data-level parallelism

Abstract This paper presents several optimization algorithms for a High Efficiency Video Coding (HEVC) encoder based on single instruction multiple data (SIMD) operations and data-level parallelism. Based on the analysis of the computational complexity of HEVC encoder, we found that interpolation filter, cost function, and transform take around 68% of the total computation, on average. In this paper, several software optimization techniques, including frame-level interpolation filter and SIMD implementation for those computationally intensive parts, are presented for a fast HEVC encoder. In addition, we propose a slice-level parallelization and its load-balancing algorithm on multi-core platforms from the estimated computational load of each slice during the encoding process. The encoding speed of the proposed parallelized HEVC encoder is accelerated by approximately ten times compared to the HEVC reference model (HM) software, with minimal loss of coding efficiency.

Eclat Algorithm for FIM on CPU-GPU co-operative & parallel environment

Extracting the frequent itemsets from a transactional database is a fundamental task in data mining field because of its broad applications in mining association rules, time series, correlations etc. The Apriori or Eclat approaches are the commonly used generate-and-check approach to obtain frequent itemsets from a database with a given threshold value. Implementations take advantage of the GPU's massively multi-threaded SIMD (Single Instruction, Multiple Data) architecture which will employ a bitmap data structure to represent vertical transaction list ,to exploit the GPU's SIMD parallelism , and to perform the support counting operation. The implementation runs entirely on the GPU and eliminates intermediate data transfer between the GPU memory and the CPU memory, which can reduce computation time and improve overall performance .OpenCL is a platform independent Open Computing Language for GPU computation. Thus, the aim of our approach is to develop efficient parallel new advanced Eclat strategy of Frequent Itemset Mining that utilize new-generation graphics processing units (GPUs) to speed-up the process.

CuSora: Real-time software radio using multi-core graphics processing unit

The Sora platform, which is a fully programmable, high-performance software radio platform based on a commodity general purpose PC, has recently received significant attention. However, acceleration techniques used in Sora are too complicated for developers, which can prevent researchers from modifying physical layer (PHY) processing. This paper presents the CuSora platform, which integrates the Sora platform with a popular multi-core graphics processing unit (GPU) as the modem processor to achieve high-speed PHY signal processing. CuSora also exploits software techniques to fulfill requirements for real-time communication. A software controller is presented to achieve multi-mode communication. The features of the single-instruction multiple data parallel computation of the GPU are also employed to accelerate PHY processing. Several wireless protocols, such as WiFi (802.11a) or WiMAX (802.16), are demonstrated on the CuSora platform for verification. CuSora meets the requirement of real-time communication and has an excellent bit error ratio performance. CuSora has a higher performance, shorter development cycle, and better coding flexibility than the Sora platform.

Data Parallel density‐based genetic clustering on CUDA Architecture

SUMMARYEvolutionary clustering algorithms have been proven as a good ability to find clusters in data. Among their advantages belong the abilities to adapt to data and to determine the number of clusters automatically, thus requiring less a priori assumptions about analyzed objects than traditional clustering methods. Unfortunately, such a clustering by genetic algorithms and evolutionary algorithms in general suffers from high computational costs when it comes to recurrent fitness function evaluation. Computing on graphic processing units (GPUs) is a recent programming and development paradigm bringing high performance parallel computing closer to general audience. Modern general purpose GPUs are composed of tens to thousands of computational cores that can execute programs in parallel using the single instruction multiple data parallel processing approach. General purpose GPU programs need to be designed and implemented in a data parallel way and with respect to the architecture of target devices to fully utilize their high performance. This study presents a design, implementation, and evaluation of a data parallel genetic algorithm for density‐based clustering. The algorithm was implemented and evaluated on the nVidia Compute Unified Device Architecture (CUDA) platform. Copyright © 2013 John Wiley & Sons, Ltd.

A flexible algorithm for calculating pair interactions on SIMD architectures

Calculating interactions or correlations between pairs of particles is typically the most time-consuming task in particle simulation or correlation analysis. Straightforward implementations using a double loop over particle pairs have traditionally worked well, especially since compilers usually do a good job of unrolling the inner loop. In order to reach high performance on modern CPU and accelerator architectures, single-instruction multiple-data (SIMD) parallelization has become essential. Avoiding memory bottlenecks is also increasingly important and requires reducing the ratio of memory to arithmetic operations. Moreover, when pairs only interact within a certain cut-off distance, good SIMD utilization can only be achieved by reordering input and output data, which quickly becomes a limiting factor. Here we present an algorithm for SIMD parallelization based on grouping a fixed number of particles, e.g. 2, 4, or 8, into spatial clusters. Calculating all interactions between particles in a pair of such clusters improves data reuse compared to the traditional scheme and results in a more efficient SIMD parallelization. Adjusting the cluster size allows the algorithm to map to SIMD units of various widths. This flexibility not only enables fast and efficient implementation on current CPUs and accelerator architectures like GPUs or Intel MIC, but it also makes the algorithm future-proof. We present the algorithm with an application to molecular dynamics simulations, where we can also make use of the effective buffering the method introduces.

A compiler framework for extracting superword level parallelism

SIMD (single-instruction multiple-data) instruction set extensions are quite common today in both high performance and embedded microprocessors, and enable the exploitation of a specific type of data parallelism called SLP (Superword Level Parallelism). While prior research shows that significant performance savings are possible when SLP is exploited, placing SIMD instructions in an application code manually can be very difficult and error prone. In this paper, we propose a novel automated compiler framework for improving superword level parallelism exploitation. The key part of our framework consists of two stages: superword statement generation and data layout optimization. The first stage is our main contribution and has two phases, statement grouping and statement scheduling, of which the primary goals are to increase SIMD parallelism and, more importantly, capture more superword reuses among the superword statements through global data access and reuse pattern analysis. Further, as a complementary optimization, our data layout optimization organizes data in memory space such that the price of memory operations for SLP is minimized. The results from our compiler implementation and tests on two systems indicate performance improvements as high as 15.2% over a state-of-the-art SLP optimization algorithm.

Compiler supports for VLIW DSP processors with SIMD intrinsics

SUMMARYTo sustain growing multimedia workload, modern digital signal processing (DSP) processors are commonly equipped with subword instructions to accelerate signal processing. Besides subword, functional units of very long instruction word (VLIW) DSP processors can also be employed to process multiple data streams in parallel. However, because of power and area concerns, many embedded VLIW DSP processors adopt distributed register files to reduce read/write ports and wire connection by privatizing register files for clusters and even for functional units. The distributed design presents great challenges to compilers in distributing single instruction, multiple data (SIMD) workload to functional units. In this paper, we address the issue in supporting SIMD parallelism on VLIW DSP processors with subword instructions and distributed register files. Currently, industrial practices have adopted intrinsics that enable developers to utilize hardware resources and compete with hand‐coded assembly in performance. However, it is still an open issue to provide such a solution for VLIW DSP processors with distributed register files. In this work, we provide SIMD intrinsics to allow programmers to write highly optimized codes by following given programming guides. In addition, an enhanced register allocation scheme and data replication optimizations are devised to enable efficient code generation. In our experiments, DSPstone benchmark and a set of H.264 kernels are used to evaluate the proposed programming and optimization schemes. The result shows that by combining SIMD intrinsics and compiler optimizations, one is able to obtain remarkable performance improvements, speedups of 2.9 and 3.5 for DSPstone and H.264 kernels, respectively. Copyright © 2011 John Wiley & Sons, Ltd.

A Scalable Massively Parallel Processor for Real-Time Image Processing

This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high performance of 191 GOPS, a high power efficiency of 310 GOPS/W, and a high area efficiency of 31.6 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The applied pipeline architecture is optimized to reduce the number of controller overhead cycles so that the SIMD parallel processing unit can be utilized during up to 99% of the operating time of typical application programs. The processor can be also optimized for low cost, low power, and high performance multimedia system-on-a-chip (SoC) solutions. A combination of custom and automated implementation techniques enables scalability in the number of PEs. The processor has two operating modes, a normal frequency (NF) mode for higher power efficiency and a double frequency (DF) mode for higher performance. The combination of high area efficiency, high power efficiency, high performance, and the flexibility of the SIMD processor described in this paper expands the application of real-time image processing technology to a variety of electronic devices.

임베디드 병렬 프로세서를 위한 픽셀 서브워드 병렬처리 명령어 구현

프로세서 기술은 공정비용의 증가와 전력 소모 때문에 단순 동작 주파수를 높이는 방법이 아닌 다수의 프로세서를 집적하는 병렬 프로세싱 기술 발전이 이루어지고 있다. 본 논문에서는 멀티미디어에 내재한 무수한 데이터를 효과적으로 처리할 수 있는 SIMD(Single Instruction Multiple Data) 기반 병렬 프로세서를 소개하고, 또한 이러한 SIMD 기반 병렬 프로세서 아키텍처에서 이미지/비디오 픽셀을 효율적으로 처리 가능한 픽셀 서브워드 병렬처리 명령어를 제안한다. 제안하는 픽셀 서브워드 병렬처리 명령어는 48비트 데이터패스 아키텍처에서 4개의 12비트로 분할된 레지스터에 4개의 8비트 픽셀을 저장하고 동시에 처리함으로써 기존의 멀티미디어 전용 명령어에서 발생하는 오버플로우 및 이를 해결하기 위해 사용되는 패킹/언팽킹 수행의 상당한 오버헤드를 줄일 수 있다. 동일한 SIMD 기반 병렬 프로세서 아키텍처에서 모의 실험한 결과, 제안한 픽셀 서브워드 병렬처리 명령어는 baseline 프로그램보다 2.3배의 성능 향상을 보인 반면, 인텔사의 대표적인 멀티미디어 전용 명령어인 MMX 타입 명령어는 baseline 프로그램보다 단지 1.4배의 성능 향상을 보였다. 또한, 제안한 명령어는 baseline 프로그램보다 2.5배의 에너지 효율 향상을 보인 반면, MMX 타입 명령어는 baseline 프로그램보다 단지 1.8배의 에너지 효율 향상을 보였다. Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of <TEX>$2.3{\times}$</TEX> over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only <TEX>$1.4{\times}$</TEX> over the same baseline SIMD array performance. In addition, the proposed instructions achieve <TEX>$2.5{\times}$</TEX> better energy efficiency than the baseline program, while MMX-type instructions achieve only <TEX>$1.8{\times}$</TEX> better energy efficiency than the baseline program.

Partial wave analysis using graphics processing units

Partial wave analysis is an important tool for determining resonance properties in hadron spectroscopy. For large data samples however, the un-binned likelihood fits employed are computationally very expensive. At the Beijing Spectrometer (BES) III experiment, an increase in statistics compared to earlier experiments of up to two orders of magnitude is expected. In order to allow for a timely analysis of these datasets, additional computing power with short turnover times has to be made available. It turns out that graphics processing units (GPUs) originally developed for 3D computer games have an architecture of massively parallel single instruction multiple data floating point units that is almost ideally suited for the algorithms employed in partial wave analysis. We have implemented a framework for tensor manipulation and partial wave fits called GPUPWA. The user writes a program in pure C++ whilst the GPUPWA classes handle computations on the GPU, memory transfers, caching and other technical details. In conjunction with a recent graphics processor, the framework provides a speed-up of the partial wave fit by more than two orders of magnitude compared to legacy FORTRAN code.

Guest Editorial: Special Issue on Computing Architectures for Real-Time Video/Image Analysis

In recent years, video and image analysis tools have been increasingly employed in many real-time applications; these include lane and car recognition for intelligent transportation systems, human object segmentation and tracking for intelligent video surveillance systems, and face detection and image indexing for digital still cameras and camcorders. To implement these analysis tools in real-time applications, new computing architectures such as reconfigurable architectures, application-specific instruction-set processors, stream processing architectures, and dedicated processing elements have been developed to handle more complex real-time content analysis. It is often necessary to integrate specially designed hardware accelerators with other processors to achieve a high processing speed. Furthermore, new algorithms that are suitable for hardware design or implementation on existing architectures play important roles in such systems. The purpose of this special issue is to report on new hardware design ideas to support these video and image analysis tools. This special issue contains two parts. The first part describes computing platform design, including vision processors and memory sub-system design. The second part describes several design case studies of image and video analysis systems, including machine learning engines and video segmentation engines. The first part begins with two general-purpose vision processors with a single-instruction-multiple-data (SIMD) architecture that have been developed in the industry. These two new-generation designs both feature enhanced capabilities for processing higher-level video analysis tasks with different schemes. In “IMAPCAR: A 100 GOPS In-vehicle Vision Processor Based on 128 Ring Connected 4-Way VLIW Processing Elements,” Kyo and Okazaki design an in-vehicle vision processor with 128 8-bit four-way verylong-instruction-word (VLIW) RISC processing element (PE) array architecture. As compared to their previous design, IMAP-CE, the new design realizes 2.5 times better performance via the improved video I/O flexibility and data remapping structure, addition of one MAC unit per PE, and increased reliability of memory structure. In “Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis,” Abbo, Kleihorst, and Schueler design a 140 GOPS image processor with a massively parallel SIMD (MP-SIMD) architecture comprising 320 PEs arranged as a linear processor array. To support regionbased processing, it provides a low-cost look-up table (LUT) and flag aggregation and flag-based result selection. In addition to computation engines, the design of memory sub-systems also plays an important role in a video and image analysis system. In “Streaming Data Movement for Real-Time Image Analysis,” Lopez-Lagunas and Chai propose the notion of stream descriptors as a means to define image stream access patterns and to improve memory access efficiencies by discovering the locality between different data streams. Examples are provided with a Reconfigurable Streaming Vector Processor (RSVP), and the design concept can be widely applied on different computing platforms such as ASIC and reconfigurable hardware. The second part describes four case studies that target different computing platforms: FPGA, multi-core processor, reconfigurable processor, and hybrid computing platform. S.-Y. Chien (*) National Taiwan University, Taipei, Taiwan e-mail: sychien@cc.ee.ntu.edu.tw