Single Flux Quantum Research Articles

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

This paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.6~\mu W$ </tex-math></inline-formula> and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

VHDL models of the basic dual-rail asynchronous RSFQ gates

This paper presents a basic approach for applying Very High-Speed Integrated Circuits Hardware Description Language (VHDL) descriptions of dual-rail rapid single flux quantum circuits (RSFQ). Because RSFQ is naturally pulsed, dual-rail data encoding encourages event driven data processing at very high speeds. A method for suitable simulation models of the basic asynchronous RSFQ gates is described. The realization of VHDL models is performed in relation with the subsequent implementation for simulation and parameter optimization of complex logic cells.

A Hybrid Josephson Transmission Line and Passive Transmission Line Routing Framework for Single Flux Quantum Logic

The single flux quantum (SFQ) logic family is a novel digital logic as it provides ultrafast and energy-efficient circuits. For large-scale SFQ circuit design, specialized electronic design automation (EDA) tools are required due to the differences in logic type, timing constraints, and circuit architecture, in contrast to the Complementary metal–oxide–semiconductor (CMOS) logic. In order to improve the overall performance of an SFQ circuit, an efficient routing algorithm should be applied during the layout design to perform accurate timing adjustment for fixing hold violations and optimizing critical paths. Thus, a hybrid Josephson transmission line and passive transmission line routing framework is proposed. It consists of four main modules and an exploration of the potential timing performance based on the given layout placement. The proposed routing tool is demonstrated on seven testbench circuits. The obtained results demonstrate that the operating frequency is greatly improved, and all the hold violations are eliminated for each circuit.

Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> . We discuss future steps to improve the SB technique.

Optimization of Suzuki Stack Circuit to Reduce Power Dissipation

Superconductor–semiconductor hybrid circuits can combine the benefits of the high-speed and low-power operation of single-flux quantum circuits and high integration densities of CMOS technology such as memory. The Suzuki stack, a type of Josephson latching driver/amplifier, is a widely used interface circuit in Josephson–CMOS hybrid memories. Due to the limited cooling power at cryogenic temperatures, the power dissipation is becoming an important concern, especially in large-scale systems. An optimization technique to significantly reduce the power dissipation of Suzuki stack circuits is proposed in this article. The proposed design can reduce the power dissipation by 30–70% while causing a voltage drop of 2–9% in the output voltage depending on the circuit parameter configuration. The tradeoffs between the power dissipation and output voltage characteristics are discussed. The proposed design can operate correctly within at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 20% of process parameter variations as demonstrated with extensive simulations.

On-chip test vector generation and downsampling for testing RSFQ circuits

An on-chip high-frequency testing method for rapid single flux quantum circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.

QuCTS—Single-Flux Quantum Clock Tree Synthesis

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time.

Extended FDTD Method for Coanalysis of Superconducting Passive Transmission Lines and Josephson Junction Drivers and Receivers

In rapid single-flux quantum circuits, the signal integrity problem of superconducting passive transmission lines (PTLs) becomes critical. In this article, an extended 3-D finite-difference time-domain (FDTD) method is proposed for coanalysis of superconducting PTLs and Josephson junction (JJ) drivers and receivers. The central difference FDTD scheme is used for PTLs, and the backward difference method is adopted for JJs, which are introduced to FDTD cells as lumped elements. Due to the nonlinearity of JJs, the Newton–Raphson method is introduced to solve the boundary condition of the FDTD method. Compared with the 1-D FDTD method of the transmission line model of PTLs, the proposed method performs full-wave analysis of the physical structure of PTLs. Therefore, the proposed 3-D FDTD method is theoretically more accurate than the conventional method by avoiding parameter extraction and circuit analysis.

Nonvolatile memory cell using a superconducting-ferromagnetic π Josephson junction

Storage of a single magnetic flux quantum in a superconducting loop containing a Josephson junction represents a promising unit cell configuration for construction of a cryogenic memory of superconducting digital circuits. However, application of a DC bias current is required for operation of such a memory cell to maintain trapping of the flux quantum in the storage loop. In this work, we present a superconducting memory cell that uses a superconducting-magnetic π junction. The cell characteristics show flux quantum hysteresis centering at the zero-bias current. We develop a fabrication process that combines superconductor–ferromagnet–superconductor (SFS) junctions with superconductor–normal metal–superconductor (SNS) junctions. The critical current density of the SFS junctions shows a 0–π oscillation as a function of the ferromagnetic layer thickness. The formation of the π junction is confirmed further by the flux modulation curves of a superconducting quantum interference device made from SNS junctions with an additional SFS junction.

Braiding Operations for a Topological Josephson Junction Array using SFQ Current Pulses

Majorana bound states (MBSs) can occur in topological Josephson junction (JJ) arrays with the presence of a fractional vortex with 2π-phase winding. It has been theoretically shown that the braiding operation can be achieved by using current pulses, compatible with single flux quantum (SFQ) technology. Therefore, we designed an SFQ logic circuit for the braiding operations of the topological JJ array using single flux quanta in a conventional JJ array. Braiding operations could be realized by an SFQ logic circuit with double flux quantum driver. To obtain positive and negative current pulses using the SFQ logic circuit, we used SFQ logic circuits with ac biasing for simulation. Finally, we confirmed the CNOT operation using an array-type SFQ circuit by means of simulation and estimated the CNOT operation speed.

Operation of a 4-bit RSFQ digital-to-analog converter based on a binary split-confluence configuration

One of the unique applications of single-flux-quantum (SFQ) circuitry is a digital-to-analog converter (DAC) of which the output voltage is defined by the Josephson effect. Recently, we have designed and operated rapid single-flux-quantum (RSFQ) DACs with frequency modulation of SFQ pulse sequences. In this paper, we report our design and test results of a 4-bit RSFQ-DAC based on the configuration of the “sum of selected bits sequence (Σ-SBS)”. By adjusting the timing margins, in addition to the fabrication using the Nb integration process with the critical current density as high as 10 kA/cm2, the maximum output voltage up to 260 μV was demonstrated.

Flux Mitigation in Wide Superconductive Striplines

The increasing complexity of modern superconductive circuits, and single flux quantum (SFQ) circuits in particular has made the issue of flux trapping of growing importance. The use of wide superconductive striplines for signal routing has exacerbated this issue. Trapping residual magnetic fields in these striplines degrades performance while reducing margins, damaging the operability of superconductive circuits. In this article, an area efficient topology for striplines is introduced to manage flux trapping in large scale SFQ circuits. This topology is composed of narrow parallel lines in series with small resistors. The proposed topology decreases the length of the striplines by exploiting the mutual inductance between the narrow parallel lines. The topology requires significantly less area while preventing flux trapping within wide superconductive striplines. The narrow parallel line topology also reduces coupling capacitance between striplines. The proposed approach is compatible with automated routing of large scale SFQ integrated circuits.

An Electromagnetic-Flux-Distribution Model for Analyses of Superconducting Josephson Junction Circuits and Quantum Phase-Slip Junction Circuits

The Josephson junctions have brought the developments of superconducting quantum interference devices (SQUIDs) and the single-flux quantum (SFQ) digital integrated circuits. Meanwhile, the quantum phase-slip (QPS) junction is founded to be the dual element of the Josephson junction and is promising for the new devices dual to the Josephson junction circuits. This article presents a general electromagnetic-flux distribution model with the conventional electric variables to unify the analysis methods for the superconducting circuits based on the Josephson junctions and QPS junctions. This model depicts the working principles of the Josephson junction network and its dual circuit with the uniform circuit equations; it also provides the general solution of building the dual circuit of a Josephson junction network with QPS Junctions. The analyses of a Josephson junction network and its dual circuit are demonstrated, and the simulation results based on the electromagnetic-flux distribution model are presented. The general electromagnetic-flux distribution model bridges the gap between the superconducting and non-superconducting circuits.

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal that incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point that renders the conventional design flow of placement followed by clock tree synthesis (CTS) ineffective to obtain a high quality clock tree with low clock skew. Moreover, very few works in the literature attempted to minimize the maximum path length during SFQ circuit placement. The maximum path length, which is the length of the longest source-to-sink path of any data signal, should be minimized to achieve a higher final performance and to reduce the overhead for length matching in subsequent routing. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by CTS and clock splitter insertion, and then, performs a second stage of global placement to replace both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is resynthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. We propose a novel net model in global placement that facilitates the concurrent optimization of the total wirelength and the maximum path length. After legalizing the placement of all cells, a specialized placement refinement method is run to further reduce the clock skew and the maximum path length. Compared with the previous state-of-the-art work, on average, we reduced the total half-perimeter wirelength by 9%, reduced the maximum path length by 58%, and reduced the clock skew by 32%.

Compact Stochastic Computing Circuits Using the Latching Function of RSFQ Circuits for Computing Polynomials

Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

Superconducting single flux quantum (SFQ) technology for power-efficiency computing

Superconducting single flux quantum (SFQ) technology for power-efficiency computing

A new LFSR based high-frequency test method for RSFQ circuit

Rapid single flux quantum (RSFQ) circuits have the advantages of high speed and low power consumption. The typical frequency of the RSFQ circuits is tens of GHz. Therefore, it is necessary to reliably test the high-frequency performance of RSFQ circuits simply and effectively. This paper proposes a new on-chip high-frequency testing method, which uses pseudo-random sequences generated by linear feedback shift register (LFSR) as the test vectors, and the output shift registers (SRs) to store the last piece of high-frequency testing result and read out it at low-frequency. Unlike the traditional high-frequency demonstration method of using the Input/Output SRs, our testing system can automatically generate a large number of test vectors to test the circuit at high frequency at low cost, making the whole high-frequency demonstration more reliable and convincing. On the other hand, this method is also a feasible and straightforward on-chip high-frequency test method for various RSFQ circuits. This work verified the proposed method, and the highest test frequency can reach 54 GHz while the circuit shows good operating margins.

Design of Discrete Hopfield Neural Network Using a Single Flux Quantum Circuit

AbstractThe superconductor single flux quantum (SFQ) logic family has been recognized as a promising candidate to resolve the energy consumption crisis in the post-Moore era, owing to its high switching speed and low power consumption. In the field of machine learning, where technology and computational require-ments are growing rapidly (e.g., image recognition and natural language processing), there is great potential for the implementa-tion of SFQ circuits. In this study, we investigate and implement a discrete Hopfield neural network (DHNN) using SFQ circuits. A DHNN is a binary neural network with less information than a standard full precision neural network; it also provides a higher processing speed. It is mainly used for pattern recognition and recovery. We designed the DHNN circuit with two patterns, each with eight elements. The circuit operates at the clock frequency of more than 50 GHz.

Pulse Interfaces and Current Management Techniques for Serially Biased RSFQ Circuits

As digital superconductor circuits based on Rapid Single Flux Quantum (RSFQ) logic scale up in complexity, so does the total current required to provide dc bias. Serial biasing (SB) is a promising solution that can be used to reduce the current by placing identical digital blocks on islands with isolated grounds and bias them sequentially. There are typically two implementations that are essential for the SB approach: the design of a driver-receiver pair (DRP) for inter-island pulse transport and the current management technique to handle the bias current flowing into and out of an island. While a DRP with good fidelity is essential for any serially biased circuit, the current management becomes critical for designs with relatively large bias current. In this paper, we address the latter. First, we propose a grapevine biasing scheme for serial bias current management. Second, we implement the technique using two exemplar circuits: the parallel counter and the digital decimation filter. We report the low and high speed test results up to 50 GHz for both circuits fabricated at MIT-LL in the SFQ5ee 10 kA&#x002F;2 &#x2126; fab node.

Surface Inductance of Superconductive Striplines

Inductance in superconductive circuits plays a significant role in rapid single flux quantum (RSFQ) systems. Inductance estimation is a challenging issue. The microwave behavior of these inductances is characterized by the surface inductance of a line. A methodology to accurately estimate the surface inductance of a stripline is the focus of this brief. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is provided. The effects of process parameter variations on the surface inductance are also discussed. An expression to model the effects of the trapezoidal geometry of a stripline is presented. The dependence of the surface inductance on the oxide and metal layer thicknesses is also presented. The objective is to provide an accurate estimate of the surface inductance for use in automated routing of VLSI complexity RSFQ circuits.