Single Field Programmable Gate Array Research Articles

All-to-all reconfigurability with sparse and higher-order Ising machines

Domain-specific hardware to solve computationally hard optimization problems has generated tremendous excitement. Here, we evaluate probabilistic bit (p-bit) based Ising Machines (IM) on the 3-Regular 3-Exclusive OR Satisfiability (3R3X), as a representative hard optimization problem. We first introduce a multiplexed architecture that emulates all-to-all network functionality while maintaining highly parallelized chromatic Gibbs sampling. We implement this architecture in a single Field-Programmable Gate Array (FPGA) and show that running the adaptive parallel tempering algorithm demonstrates competitive algorithmic and prefactor advantages over alternative IMs by D-Wave, Toshiba, and Fujitsu. We also implement higher-order interactions that lead to better prefactors without changing algorithmic scaling for the XORSAT problem. Even though FPGA implementations of p-bits are still not quite as fast as the best possible greedy algorithms accelerated on Graphics Processing Units (GPU), scaled magnetic versions of p-bit IMs could lead to orders of magnitude improvements over the state of the art for generic optimization.

SHA-256 Hardware Proposal for IoT Devices in the Blockchain Context.

This work proposes an implementation of the SHA-256, the most common blockchain hash algorithm, on a field-programmable gate array (FPGA) to improve processing capacity and power saving in Internet of Things (IoT) devices to solve security and privacy issues. This implementation presents a different approach than other papers in the literature, using clustered cores executing the SHA-256 algorithm in parallel. Details about the proposed architecture and an analysis of the resources used by the FPGA are presented. The implementation achieved a throughput of approximately 1.4 Gbps for 16 cores on a single FPGA. Furthermore, it saved dynamic power, using almost 1000 times less compared to previous works in the literature, making this proposal suitable for practical problems for IoT devices in blockchain environments. The target FPGA used was the Xilinx Virtex 6 xc6vlx240t-1ff1156.

Experimental Integration of Quantum Key Distribution and Post‐Quantum Cryptography in a Hybrid Quantum‐Safe Cryptosystem

AbstractQuantum key distribution (QKD) and post‐quantum cryptography (PQC) are the two counter measures against cryptographic attacks via quantum computing. While QKD offers information theoretic security but limited authentication scalability, PQC facilitates scalable authentication in high density networks but is not information theoretic secure. Therefore, an ideal quantum‐safe framework should efficiently leverage the complementarity of both techniques. However, despite growing efforts in integrating both, current realizations have focused on channel authentication, and a complete cryptosystem addressing both hybrid authentication and hybrid key exchange is yet to be demonstrated. Here, an authenticated hybrid key exchange protocol is introduced that incorporates PQC and QKD in a modular and information‐theoretic secure architecture. The quantum‐safe protocol is inherently resilient to catastrophic cryptographic failures and provides both forward and post‐compromise security. As proof‐of‐concept implementation, the cryptosystem on a QKD hardware prototype is integrated, with the QKD processing, PQC key exchange and secret state masking via physical unclonable functions (PUFs) all running on a single field programmable gate array (FPGA). This work paves the way for the deployment of versatile and modular quantum‐safe networks that exploit the complementarity of PQC and QKD.

Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications.

Edge artificial intelligence (AI) is receiving a tremendous amount of interest from the machine learning community due to the ever-increasing popularization of the Internet of Things (IoT). Unfortunately, the incorporation of AI characteristics to edge computing devices presents the drawbacks of being power and area hungry for typical deep learning techniques such as convolutional neural networks (CNNs). In this work, we propose a power-and-area efficient architecture based on the exploitation of the correlation phenomenon in stochastic computing (SC) systems. The proposed architecture solves the challenges that a CNN implementation with SC (SC-CNN) may present, such as the high resources used in binary-to-stochastic conversion, the inaccuracy produced by undesired correlation between signals, and the complexity of the stochastic maximum function implementation. To prove that our architecture meets the requirements of edge intelligence realization, we embed a fully parallel CNN in a single field-programmable gate array (FPGA) chip. The results obtained showed a better performance than traditional binary logic and other SC implementations. In addition, we performed a full VLSI synthesis of the proposed design, showing that it presents better overall characteristics than other recently published VLSI architectures.

A Universal Digital Lock-in Amplifier Design for Calibrating the Photo-Detector Responses with Standard Black-Bodies.

The lock-in amplifier (LIA) is widely utilized to detect ultra-weak optical periodic signals based on the phase-sensitive and enhanced detecting theory. In this paper, we present an all-digital and universal embedded LIA platform that accurately and conveniently describes the spectrum generated by standard black bodies at various temperatures with different optical detectors. The proposed design significantly reduces the complexity and cost of traditional analog LIAs while maintaining accuracy. The LIA components are implemented using a single field programmable gate array (FPGA), offering flexibility to modify parameters for different situations. The normalized mean-square error (NMSE) of the captured spectra in the experiments is within 0.9% compared the theoretical values.

Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs

Traditional High-Level Synthesis (HLS) provides rapid prototyping of hardware accelerators without coding with Hardware Description Languages (HDLs). However, such an approach does not well support allocating large applications like entire deep neural networks on a single Field Programmable Gate Array (FPGA) device. The approach leads to designs that are inefficient or do not fit into FPGAs due to resource constraints. This work proposes to shrink generated designs by coarse-grained resource control based on function sharing in functional Intermediate Representations (IRs). The proposed compiler passes and rewrite system aim at producing valid design points and removing redundant hardware. Such optimizations make fitting entire neural networks on FPGAs feasible and produce competitive performance compared to running specialized kernels for each layer.

A many-channel FPGA control system.

We describe a many-channel experiment control system based on a field-programmable gate array (FPGA). The system has 16 bit resolution on 10 analog 100 megasamples-per-second (MS/s) input channels, 14 analog 100 MS/s output channels, 16 slow analog input and output channels, dozens of digital inputs and outputs, and a touchscreen display for experiment control and monitoring. The system can support ten servo loops with 155ns latency and MHz bandwidths, in addition to as many as 30 lower bandwidth servos. We demonstrate infinite-impulse-response (IIR) proportional-integral-differential filters with 30ns latency by using only bit-shifts and additions. These IIR filters allow timing margin at 100 MS/s and use fewer FPGA resources than straightforward multiplier-based filters, facilitating many servos on a single FPGA. We present several specific applications: Hänsch-Couillaud laser locks with automatic lock acquisition and a slow dither correction of lock offsets, variable duty cycle temperature servos, and the generation of multiple synchronized arbitrary waveforms.

A Case for Low-Cost Personal Electronic Laboratory Equipment using FPGAs

The field of reconfigurable computing is gaining a lot of following, and several use cases have been developed for it. At the centre of reconfigurable computing is the field programmable gate array (FPGA) due to its computational speed and versatility. The goal of the work reported here was to show that a single FPGA board paired with a computer monitor can be used as the sole laboratory equipment in a cash-strapped educational institution or by an individual. A Terasic DE1-SoC board was programmed as an oscilloscope, and digital multimeter. In keeping with the low-cost theme of this work, no external signal conditioning circuit was used and the on-board LTC2308 ADC was used for signal acquisition. At frequencies below 15 kHz, the voltage measurements of the developed FPGA lab instrument had a mean error of 58 mV. The voltage measurement errors, however, increased with an increase in frequency and the errors were significant when the signal frequencies exceeded 100 kHz. In terms of the use of the FPGA to replace multiple lab instruments, 13% of the DSPs on the FPGA were used for the implementation and 80% of the Adaptive logic modules. We therefore demonstrate that with $300 dollars, multiple pieces of laboratory equipment can be replaced by a single FPGA board and a monitor.

Accurate Multi-Channel QCM Sensor Measurement Enabled by FPGA-Based Embedded System Using GPS

This paper presents a design and implementation proposal for a real-time frequency measurement system for high-precision, multi-channel quartz crystal microbalance (QCM) sensors using a field programmable gate array (FPGA). The key contribution of this work lies in the integration of a frequency measurement and mass resolution computation based on Global Positioning System (GPS) signals within a single FPGA chip, utilizing Input/Output Blocks to incorporate logic QCM oscillator circuits. The FPGA design enables parallel processing, ensuring accurate measurements, faster calculations, and reduced hardware complexity by minimizing the need for external components. As a result, a cost-effective and accurate multi-channel sensor system is developed, serving as a reconfigurable standalone measurement platform with communication capabilities. The system is implemented and tested using the FPGA Xilinx Virtex-6, along with multiple QCM sensors. The implementation on a Xilinx XC6VLX240T FPGA achieves a maximum frequency of 324 MHz and consumes a dynamic power of 120 mW. Notably, the design utilizes a modest number of resources, requiring only 188 slices, 733 flip-flops, and 13 IOBs to perform a double-channel sensor microbalance. The proposed system meets the precision measurement requirements for QCM sensor applications, exhibiting low measurement error when monitoring QCM frequencies ranging from 1 to 50 MHz, with an accuracy of 0.2 ppm and less than 0.1 Hz.

Distributed large-scale graph processing on FPGAs

Processing large-scale graphs is challenging due to the nature of the computation that causes irregular memory access patterns. Managing such irregular accesses may cause significant performance degradation on both CPUs and GPUs. Thus, recent research trends propose graph processing acceleration with Field-Programmable Gate Arrays (FPGA). FPGAs are programmable hardware devices that can be fully customised to perform specific tasks in a highly parallel and efficient manner. However, FPGAs have a limited amount of on-chip memory that cannot fit the entire graph. Due to the limited device memory size, data needs to be repeatedly transferred to and from the FPGA on-chip memory, which makes data transfer time dominate over the computation time. A possible way to overcome the FPGA accelerators’ resource limitation is to engage a multi-FPGA distributed architecture and use an efficient partitioning scheme. Such a scheme aims to increase data locality and minimise communication between different partitions. This work proposes an FPGA processing engine that overlaps, hides and customises all data transfers so that the FPGA accelerator is fully utilised. This engine is integrated into a framework for using FPGA clusters and is able to use an offline partitioning method to facilitate the distribution of large-scale graphs. The proposed framework uses Hadoop at a higher level to map a graph to the underlying hardware platform. The higher layer of computation is responsible for gathering the blocks of data that have been pre-processed and stored on the host’s file system and distribute to a lower layer of computation made of FPGAs. We show how graph partitioning combined with an FPGA architecture will lead to high performance, even when the graph has Millions of vertices and Billions of edges. In the case of the PageRank algorithm, widely used for ranking the importance of nodes in a graph, compared to state-of-the-art CPU and GPU solutions, our implementation is the fastest, achieving a speedup of 13 compared to 8 and 3 respectively. Moreover, in the case of the large-scale graphs, the GPU solution fails due to memory limitations while the CPU solution achieves a speedup of 12 compared to the 26x achieved by our FPGA solution. Other state-of-the-art FPGA solutions are 28 times slower than our proposed solution. When the size of a graph limits the performance of a single FPGA device, our performance model shows that using multi-FPGAs in a distributed system can further improve the performance by about 12x. This highlights our implementation efficiency for large datasets not fitting in the on-chip memory of a hardware device.

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA.

Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability that allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify that the image quality was not compromised for speed.

A Domain-Specific Accelerator for Ultralow Latency Market Data Distribution System

Ultralow latency parsing of financial data is gaining significance in the high-frequency trading of the security exchange market. Hardware-aided systems exhibit superior improvement of latency over traditional software solutions, but flexibility may suffer when processing the financial protocol. This article presents a domain-specific accelerator for the market data distribution system, which integrates a financial information exchange adapted for streaming (FAST) decoder, a 10-Gbps network interface, and a high-speed PCIe host interface into a single field programmable gate array (FPGA) acceleration card. The proposed FAST decoder adopts the finite state machines-coordinated sequence mapping table to achieve run-time reconfigurability over fine-grained FPGA programming, and 16 fields can be decoded simultaneously in a pipelined manner, resulting in a decoding latency of only 33 ns. Evaluated on the Xilinx Alveo U200 acceleration card, this work improves the latency of decoding a FAST message by 26%–72% than state-of-the-art FPGA designs, and outperforms the software baseline by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&gt;27\times$</tex-math></inline-formula> in terms of latency covering both decoding and communication.

An FPGA-Based Hierarchical Parallel Real-Time Simulation Method for Cascaded Solid-State Transformer

The cascaded H-bridge (CHB)-based solid-state transformer (SST) is a core interface device for power conversion in the distribution network. However, the complicated structures and higher switching frequencies bring significant challenges to real-time simulation and hardware-in-loop (HIL) testing. This article proposes a field-programmable gate array (FPGA)-based hierarchical parallel real-time simulation method for cascaded SST, which mainly includes highly parallel solving at the operation level, module level, and system level. A dual-port equivalent model of the cascaded SST is constructed based on the hierarchical parallel real-time simulation method. A cascaded SST containing 42 modules (630 components) can be simulated on a single FPGA with a minimum of 400 ns time-step. The information of the ports of the equivalent model and the information of the internal nodes of the cascaded SST can be obtained, which is the same as the simulation of detailed model. The real-time simulation of cascaded SST with input-series-output-parallel (ISOP) structure is carried out on a Xilinx Kintex-7 FPGA. The simulation results show that the real-time simulation waveforms are almost consistent with those in PSCAD/EMTDC software package.

An Ultracompact Underwater Pulsed Digital Holographic Camera With Rapid Particle Image Extraction Suite

This article presents the design, development, and testing of an ultracompact underwater pulsed digital holographic camera (named weeHoloCam) that has been successfully deployed in the North Sea. With a footprint of 9 cm diameter × 60 cm long and weighing just 3.5 kg, to our knowledge, this is the lightest and most compact system of its kind in the world. It can be easily adapted for mounting on remotely operated underwater vehicles (ROVs) and autonomous underwater vehicles (AUVs). weeHoloCam can record 12 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> of the water column per hologram at 20 Hz and has a capacity to continuously record up to 200 000 holograms, each 5 MB in size. Along with the holographic camera, a field-programmable gate array (FPGA)-accelerated hologram analysis suite has been developed. The 838 megapixel/s reconstruction speed demonstrated is the highest reported speed for a single FPGA implementation to date. This is an extremely important development as rapid processing of recorded holograms is vital for the viability of subsea holographic cameras. weeHoloCam was successfully trialed in the North Sea, recording close to a hundred thousand holograms and extracting particle images within those holograms at a rate of 190 per min. weeHoloCam has the potential to play an important role in several oceanic studies: spatial and temporal monitoring of plankton species; study of plankton dynamics; study of vertical transport of floc; and monitoring microplastic pollution in the ocean, to name but a few.

Ultrafast ultrasound beamformer for plane wave imaging with field programmable gate array

In this work, we propose a novel method of implementing an ultrafast ultrasound beamformer for plane wave imaging (PWI) on a field programmable gate array (FPGA). First, a modified delay calculation method was proposed to (1) separate the transmit and receive delay, (2) reduce the size of delay profile, and (3) enable parallel beamforming by delay reuse and data vectorization. Second, a parallelized implementation of beamformer on single FPGA was proposed by (1) loading pre-calculated delay profile from external memory instead of calculating delay on run-time, (2) vectorizing channel data fetching, (3) compensating transmit and receive delays separately, and (4) using fixed summing networks to reduce consumption of logic resources. The proposed method was also highly scalable, which was demonstrated by implementing the beamformer with different beamforming rates ranging from 2.4 G to 9.6 G samples per second to three different sizes of FPGAs ranging from entry-level FPGA to high-end FPGA. The power consumption was less than 3 watts for 2.4 G samples per second beamforming rate, which demonstrates the possibility of implementing ultrafast ultrasound imaging on handheld probe. The FPGA beamformer’s results were compared with Verasonics CPU beamformer’s result to verify that the image quality was not compromised for speed.

Cost-Effective Network Reordering Using FPGA

The advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, demanding low latency and high throughput. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. In addition, existing network reordering solutions become less applicable due to the drastic changes in the type of network endpoints, as IoT devices typically have less memory and are likely to be power-constrained. One approach to address this problem is reordering packets using reconfigurable hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network endpoints due to their high performance and flexibility. Moreover, previous research on packet reordering using FPGAs has serious design flaws that can lead to unnecessary packet dropping due to blocking in memory. This research proposes a scalable hardware-focused method for packet reordering that can overcome the flaws from previous work while maintaining minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip.

An Optimized Multi-layer Spiking Neural Network implementation in FPGA Without Multipliers

This paper presents an expansion and evaluation of the hardware architecture for the Optimized Deep Event-driven Spiking Neural Network Architecture (ODESA). ODESA is a state-of-the-art, event-driven multi-layer Spiking Neural Network (SNN) architecture that offers an end-to-end, online, and local supervised training method. In previous work, ODESA was successfully implemented on Field-Programmable Gate Array (FPGA) hardware, showcasing its effectiveness in resource-constrained hardware environments. Building upon the previous implementation, this research focuses on optimizing the ODESA network hardware by introducing a novel approach. Specifically, we propose substituting the dot product multipliers in the Neurons with a low-cost shift-register design. This optimization strategy significantly reduces the hardware resources required for implementing a neuron, thereby enabling more complex SNNs to be accommodated within a single FPGA. Additionally, this optimization results in a reduction in power consumption, further enhancing the practicality and efficiency of the hardware implementation. To evaluate the effectiveness of the proposed optimization, extensive experiments and measurements were conducted. The results demonstrate the successful reduction in hardware resource utilization while maintaining the network's functionality and performance. Moreover, the power consumption reduction contributes to the overall energy efficiency of the hardware implementation.

Real-time FPGA prototyping of a 15GBaud SP-16QAM coherent optical receiver with optimal interpolating for clock recovery and equalization.

We demonstrate a real-time coherent optical receiver based on a single field programmable gate array (FPGA) chip. To strike the balance between the performance and hardware resources, we use a clock recovery scheme using the optimal interpolation (OI). The performance and complexity of the OI-based scheme and the traditional schemes are compared and discussed via offline digital signal processing. And a real-time 15GBaud single-polarization 16QAM transmission experiment under different received optical power using the FPGA-based receiver is carried out to demonstrate the overall performance of different clock recovery and equalization schemes. The result proves that, compared to the traditional scheme with a cubic interpolator and a 7-tap equalizer, the optimal interpolator significantly lowers the utilization of LUT, CARRY8, and DSP48 by 35%, 50%, and 11%, respectively, and can work properly under a received optical power of -40dBm.

Real-time adaptive ultrashort pulse compressor for dynamic group delay dispersion compensation.

The optical dispersion effect in ultrafast pulse laser systems broadens the laser pulse duration and reduces the theoretical peak power. The present study proposes an adaptive ultrashort pulse compressor for compensating the optical dispersion using a direct optical-dispersion estimation by spectrogram (DOES) method. The DOES has fast and accurate computation time which is suitable for real time controller design. In the proposed approach, the group delay dispersion (GDD) and its polarity are estimated directly from the delay marginal of the trace obtained from a single-shot frequency-resolved optical gating (FROG). The estimated GDD is then processed by a closed-loop controller, which generates a command signal to drive a linear deformable mirror as required to achieve the desired laser pulse compression. The dispersion analysis, control computation, and deformable mirror control processes are implemented on a single field programmable gate array (FPGA). It is shown that the DOES dispersion computation process requires just 0.5 ms to complete. Moreover, the proposed pulse compressor compensates for both static dispersion and dynamic dispersion within five time steps when closed-loop controller is performed at a frequency of 100 Hz. The experimental results show that the proposed pulse compressor yields an effective fluorescence intensity improvement in a multiphoton excited fluorescence microscope (MPEFM).

Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification.

A plethora of image and video-related applications involve complex processes that impose the need for hardware accelerators to achieve real-time performance. Among these, notable applications include the Machine Learning (ML) tasks using Convolutional Neural Networks (CNNs) that detect objects in image frames. Aiming at contributing to the CNN accelerator solutions, the current paper focuses on the design of Field-Programmable Gate Arrays (FPGAs) for CNNs of limited feature space to improve performance, power consumption and resource utilization. The proposed design approach targets the designs that can utilize the logic and memory resources of a single FPGA device and benefit mainly the edge, mobile and on-board satellite (OBC) computing; especially their image-processing- related applications. This work exploits the proposed approach to develop an FPGA accelerator for vessel detection on a Xilinx Virtex 7 XC7VX485T FPGA device (Advanced Micro Devices, Inc, Santa Clara, CA, USA). The resulting architecture operates on RGB images of size or sliding windows; it is trained for the “Ships in Satellite Imagery” and by achieving frequency 270 MHz, completing the inference in 0.687 ms and consuming 5 watts, it validates the approach.