Single Event Upset Tolerance Research Articles

Radiation-hardened flip-flop for single event upset tolerance

PurposeThe purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).Design/methodology/approachWith SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.FindingsSimulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.Originality/valueIn this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.

SEU Tolerance Efficiency of Multiple Layout-Hardened 28 nm DICE D Flip-Flops

Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and manufactured based on an advanced 28 nm planar technology. The systematic vertical and tilt heavy ion irradiations demonstrated that the DICE structure contributes to radiation tolerance. However, it is hard to achieve immunity from a Single Event Upset (SEU), even when a ~3-µm well isolation is utilized. The SEU mitigation of the hardened DFFs was affected by the data patterns and clock signals due to the imbalance in the number of upset nodes. When the clock signal equalled 0, no error was observed in 181Ta irradiation, indicating that the DICE DFFs are SEU tolerant in vertical irradiation owing to their reasonable isolation of sensitive volumes. The divergences of SEU cross-sections were enlarged by our specially designed joint change of tilt incidences for both the along-cell and cross-cell irradiation of heavy ions. The evaluations of SEU for both the vertical and tilt irradiations assist with eliminating the overestimation of SEU tolerance and guarantee the in-orbit safety of spacecraft in harsh radiation environments.

Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system

This paper addresses the issue of soft error mitigation for Static Random-Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) system in radiation environment to reduce their malfunction and system failure rates in space missions. Seven representative circuits are designed by using the logical resources of SRAM-based FPGA. The accelerator tests investigate that the clock distribution of the Triple Modular Redundancy (TMR) circuits is vital to achieve a high Single Event Upset (SEU) tolerance. The separated DTMR_NEW circuits are proposed to overcome the weakness of the conventional TMR circuits, and a 25× improvement of SEU tolerance for the separated DTMR_NEW circuits are verified. The statistical estimations are desirable for engineers to assess and enhance the SEU tolerance of their designed systems at earlier stages to reduce the time and development costs.

Design of a high-performance 12T SRAM cell for single event upset tolerance

Design of a high-performance 12T SRAM cell for single event upset tolerance

Single Event Upset rates in the CBC in CMS

The CMS Binary Chip (CBC) is a front-end ASIC to be used by the CMS tracker following its upgrade for High Luminosity LHC operation. It will instrument special silicon microstrip detectors to identify high transverse momentum particles in real time so tracking data can be used in the L1 trigger. The CBC should be robust against Single Event Upsets (SEUs). SEU rates have been measured in a series of tests in a 62 MeV proton beam. Each version of the chip has increased the digital circuitry, and hence the SEU susceptibility, and has also been subject to design improvements which affect SEU tolerance. The relevant design features are explained and SEU measurements reported. The expected SEU rates at the HL-LHC are estimated.

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average. INDEX TERMS Double-node upset, memory cell, radiation hardening, single event upset, soft error.

Low‐cost single event double‐upset tolerant latch design

This Letter proposes a low-cost, single event double-upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C-element (MCE) to turn off the storage cell, a three-input MCE to block the soft error from the storage cell and a weak keeper to prevent high impedance state. The storage cell in the proposed latch has better reliability than the conventional triple path dual-interlocked storage cell (TPDICE). Most up-to-date single event double-upset (SEDU) tolerant latches are carried out with too large cost penalties. The proposed one saves up to 93.32% area-power-delay product (APDP) compared with one up-to-date SEDU tolerant latch and even saves 36.36% APDP compared with only single event upset (SEU) tolerant latch in the referential. Simulation results have verified SEU and SEDU tolerance of the proposed latch.

A comparison of heavy ion induced single event upset susceptibility in unhardened 6T/SRAM and hardened ADE/SRAM

Single event upset (SEU) susceptibility of unhardened 6T/SRAM and hardened active delay element (ADE)/SRAM, fabricated with 0.35μm silicon-on-insulator (SOI) CMOS technology, was investigated at heavy ion accelerator. The mechanisms were revealed by the laser irradiation and resistor-capacitor hardened techniques. Compared with conventional 6T/SRAM, the hardened ADE/SRAM exhibited higher tolerance to heavy ion irradiation, with an increase of about 80% in the LET threshold and a decrease of ∼64% in the limiting upset cross-section. Moreover, different probabilities between 0→1 and 1→0 transitions were observed, which were attributed to the specific architecture of ADE/SRAM memory cell. Consequently, the radiation-hardened technology can be an attractive alternative to the SEU tolerance of the device-level.

Heavy Ion Characterization of Temporal-, Dual- and Triple Redundant Flip-Flops Across a Wide Supply Voltage Range in a 65 nm Bulk CMOS Process

In this paper, we investigate the single event upset (SEU) response of five D flip-flops (DFFs) employing temporal redundancy, dual redundancy, and triple modular redundancy (TMR), across a wide supply voltage range. The DFFs were designed and fabricated in a low-power commercial 65 nm bulk CMOS process and were tested using heavy ions with linear energy transfer (LET) between $\mathrm {5.1~MeV-cm^{2}/mg}$ and $\mathrm {99.1~MeV-cm^{2}/mg}$ . Results show an increasing SEU vulnerability with decreasing supply voltage, for most of the DFFs. Nevertheless, radiation tolerant topologies exhibit $14\times $ to $1328\times $ better SEU tolerance than a standard non-radiation tolerant DFF, depending on supply voltage and LET. The general observation is that at normal incidence, while taking the entire LET spectrum into account, the dual interlocked storage cell (DICE) DFF has the best SEU tolerance at supply voltages of 1 V and 0.5 V. At a supply voltage of 0.25 V, a temporal redundant DFF shows the best SEU tolerance, while the TMR DFF shows the best SEU tolerance at a supply voltage of 0.18 V. At supply voltages of 0.5 V and below, increasing the angle of incidence to 45 degrees can increase the SEU rate of the implemented DICE DFF by up to a factor of $22\times $ , making it one of the most SEU sensitive DFFs. Furthermore, utilizing high drive strength components in temporally redundant DFFs can reduce the SEU sensitivity by a factor of $3\times $ to $112\times $ , compared to when standard drive strength components are used.

Low power and high write speed SEU tolerant SRAM data cell design

As feature size scales down, reliability issues like single event upset (SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.

Study on FPGA SEU Mitigation for the Readout Electronics of DAMPE BGO Calorimeter in Space

The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of the Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based field-programmable gate array (FPGA), of which the design-level flip-flops and embedded block random access memories (RAM) are single event upset (SEU) sensitive in the harsh space environment. To comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

The last few years have seen the development and fabrication of nanoscale circuits at high density and low power. Following a single-event upset (SEU), so-called soft errors due to internal and externally induced phenomena (such as α-particles and cosmic rays in adverse environments) have been reported during system operation; this is especially deleterious for storage elements such as flip-flops. To reduce the impact of a soft error on flip-flops, hardening techniques have been utilized. This paper proposes two new slave latches for improving the SEU tolerance of a flip-flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. When used in a flip-flop, the first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16% (9%) power consumption overhead at 32-nm feature size, as compared with the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple-node upset.

Single-event upset tests on the readout electronics for the pixel detectors of the PANDA experiment

The Silicon Pixel Detector (SPD) of the future PANDA experiment is the closest one to the interaction point and therefore the sensor and its electronics are the most exposed to radiation. The Total Ionizing Dose (TID) issue has been addressed by the use of a deep-submicron technology (CMOS 0.13 μm) for the readout ASICs. While this technology is very effective in reducing radiation induced oxide damage, it is also more sensitive to Single Event Upset (SEU) effects due to their extremely reduced dimensions. This problem has to be addressed at the circuit level and generally leads to an area penalty. Several techniques have been proposed in literature with different trade-off between level of protection and cell size.A subset of these techniques has been implemented in the PANDA SPD ToPiX readout ASIC prototypes, ranging from DICE cells to triple redundancy. Two prototypes have been tested with different ion beams at the INFN-LNL facility in order to measure the SEU cross section.Comparative results of the SEU test will be shown, together with ananalysis of the SEU tolerance of the various protection schemes andfuture plans for the SEU protection strategy which will be implementedin the next ToPiX prototype.

Using Charge Accumulation to Improve the Radiation Tolerance of Multi-Gb NAND Flash Memories

Consecutive write operations on 42-nm and 60-nm single-level cell (SLC) Samsung NAND flash memories are shown to significantly improve both the total ionizing dose response and the single event upset tolerance of the memory. By writing these SLC flash memories multiple times, more charge is placed on the floating gate. This accumulated charge leads to a larger amount of radiation needed to corrupt the data. The work presented in this paper illustrates a path forward to the development of a multi-gigabit rad-hard non-volatile memory.

An SEU-hardened latch with a triple-interlocked structure

A single event upset (SEU) tolerant latch with a triple-interlocked structure is presented. Its self-recovery mechanism is implemented by using three pairs of guard-gates and inverters to construct feedback lines inside the structure. This latch effectively suppresses the effects of charge deposition at any single internal node caused by particle strikes. Three recently reported SEU-hardened latches are chosen and compared with this latch in terms of reliability. The potential problems that these three latches could still get flipped due to single event effects or single event effects plus crosstalk coupling are pointed out, which can be mitigated by this proposed latch. The SEU tolerance of each latch design is evaluated through circuit-level SEU injection simulation. Furthermore, discussions on the crosstalk robustness and some other characteristics of these latches are also presented.

SEU Tolerance Design And Implementation of A Space High Reliability Microprocessor

This paper focuses on study of a space high reliability microprocessor which is designed for space platforms, such as on-board computer systems. Space radiation environment is a special factor that should be considered when we design space high reliability processor. The architecture of Leon 3 microprocessor is investigated, which conforms to the IEEE-1754 (SPARC V8) architecture. Single-Event Effect of Leon3 is analyzed. Based on Leon3, a fault tolerance microprocessor is designed to verify Single Event Upset tolerance efforts. Expansion Hamming Code is adopted by IU and CRC is adopted by Cache to avoid some magnitude of SEU error to some degree. Inject fault in Modelsim simulator is applied to verify fault tolerance design. An FPGA platform is built to evaluate the cost and compatibility of this fault tolerance design.

Delay and Energy Analysis of SEU and SET-Tolerant Pipeline Latches and Flip-Flops

In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). This paper focuses on SEU and SET-tolerant approaches to constructing pipeline latches and flip-flops. Level-sensitive latches, edge-triggered master-slave flip-flops, and pulse-triggered flip-flops comprise the pipeline memory classes considered in this paper. TPDICE basic cells are utilized to achieve fault-tolerance and transient bypass capability. A number of single-ended and differential structures are presented and evaluated with respect to performance, energy consumption, and complexity. In addition, the SEU and SET tolerance of these structures is demonstrated. All evaluations are based off simulations performed in 90 nm CMOS. Accompanying the above evaluations, this paper also addresses concerns of multiple bit upset (MBU) affecting these designs at the 90 nm technology node. Novel hardened-by-design techniques are introduced to address these concerns, and their effectiveness is quantified.

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies[Note 1

Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to radiation-induced single-event-upsets (SEUs). Redundancy insertion has been adopted to provide the circuit with additional transient error resiliency. However, its applicability and efficiency are limited by the tight design constraints and budgets. In this paper, we present an intelligent ldquoconstraint-aware robustness insertionrdquo methodology. By selectively protecting sequential elements in static CMOS digital circuits, it is able to maximally improve the SEU tolerance while keeping the incurred design overhead within acceptable range. Our technique consists of three major components. The first one is a configurable hardening sequential cell design that serves as the basic building block of the framework; the second one is a robustness calibration technique that evaluates the relative error tolerance of all sequential elements and provides guidelines to the redundancy insertion; the third one is an optimization algorithm that searches for the optimal protection scheme under given design constraints and budgets. Simulation results show that the intelligent robustness insertion reduced the error rate by 46% with zero timing penalty and 10% area increase. Furthermore, by exploring the tradeoffs between reliability and design overhead, we also demonstrate the proposed technique can help achieve high reliability improvement while keeping the design overhead within acceptable range.

An SEU hardening approach for high-speed SiGe HBT digital logic

A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.