Heavy Ion Characterization of Temporal-, Dual- and Triple Redundant Flip-Flops Across a Wide Supply Voltage Range in a 65 nm Bulk CMOS Process

Abstract

In this paper, we investigate the single event upset (SEU) response of five D flip-flops (DFFs) employing temporal redundancy, dual redundancy, and triple modular redundancy (TMR), across a wide supply voltage range. The DFFs were designed and fabricated in a low-power commercial 65 nm bulk CMOS process and were tested using heavy ions with linear energy transfer (LET) between $\mathrm {5.1~MeV-cm^{2}/mg}$ and $\mathrm {99.1~MeV-cm^{2}/mg}$ . Results show an increasing SEU vulnerability with decreasing supply voltage, for most of the DFFs. Nevertheless, radiation tolerant topologies exhibit $14\times $ to $1328\times $ better SEU tolerance than a standard non-radiation tolerant DFF, depending on supply voltage and LET. The general observation is that at normal incidence, while taking the entire LET spectrum into account, the dual interlocked storage cell (DICE) DFF has the best SEU tolerance at supply voltages of 1 V and 0.5 V. At a supply voltage of 0.25 V, a temporal redundant DFF shows the best SEU tolerance, while the TMR DFF shows the best SEU tolerance at a supply voltage of 0.18 V. At supply voltages of 0.5 V and below, increasing the angle of incidence to 45 degrees can increase the SEU rate of the implemented DICE DFF by up to a factor of $22\times $ , making it one of the most SEU sensitive DFFs. Furthermore, utilizing high drive strength components in temporally redundant DFFs can reduce the SEU sensitivity by a factor of $3\times $ to $112\times $ , compared to when standard drive strength components are used.