Single Event Upset Cross Section Research Articles

Study of Single-Event Effects Influenced by Displacement Damage Effects under Proton Irradiation in Static Random-Access Memory

Static random-access memory (SRAM), a pivotal component in integrated circuits, finds extensive applications and remains a focal point in the global research on single-event effects (SEEs). Prolonged exposure to irradiation, particularly the displacement damage effect (DD) induced by high-energy protons, poses a substantial threat to the performance of electronic devices. Additionally, the impact of proton displacement damage effects on the performance of a six-transistor SRAM with an asymmetric structure is not well understood. In this paper, we conducted an analysis of the impact and regularities of DD on the upset cross-sections of SRAM and simulated the single-event upset (SEU) characteristics of SRAM using the Monte Carlo method. The research findings reveal an overall increasing trend in upset cross-sections with the augmentation of proton energy. Notably, the effect of proton irradiation on the SEU cross-section is related to the storage state of SRAM. Due to the asymmetry in the distribution of sensitive regions during the storage of “0” and “1”, the impact of DD in the two initial states is not uniform. These findings can be used to identify the causes of SEU in memory devices.

Exploring the impact of shrinking feature sizes on proton-induced saturation SEU cross-section through simulation

In the study reported here, Monte Carlo simulations were used to investigate single-event upsets (SEUs) induced by ultra-high-energy proton irradiation in electronic devices made with various technology nodes, and the simulation results show the following. For smaller technology nodes, the SEU cross section tends to increase when the incident proton energy exceeds 200 MeV, and the dependence of the SEU cross section on 200-MeV protons as a saturation point for technology nodes smaller than 90 nm might result in underestimated error rates. Finally, using proton SEE cross section data with energies higher than 200 MeV can better assess the severity of the non-saturation effect, and can also obtain more realistic error rate.

Deep insight on efficiency of deposited energy within sensitive volumes for characterizing basic mechanism of single event upset saturated cross-section regarding implicit inaccuracy

The Single Event Upset (SEU) characterization on the partially depleted (PD) Silicon-On-Insulator (SOI) SRAMs manufactured by 0.5/0.35 μm CMOS technology has been studied by using the experimental accelerator’s testing and Monte Carlo simulation. The results show that, in spite of the good consistent between the simulated data and experimental testing, one notable phenomenon is that, linear energy transfer (LET) as the input has no manifest influence on the saturation of SEU cross-section. This non-negligible trend led us to use the term ion velocity instead of LET. The characteristics of ion velocity have certainly been proved by the experiment, while the unsimilar results are found for the simulation with no any difference from the SEU cross-section. Consequently, a more straightforward calculation in the deposited energy within sensitive volume (SV) has performed by inspecting directly into the underlying mechanism of the undetected energy loss. The loss of deposited energy has been obtained in the assumption that the heavy ions strike on the hypothetical device at oblique incidence. The unexpected energy loss resulted from incident ions at oblique incidence as edge effect indicates the importance of quantifying the efficiency of energy collection with respect to the dimensions of SV, including the variance of surface area and thickness. It is illustrated that the deposited energy induced by heavy ions on the condition of changeable surface area has more sensitivity on the incident angle and ionic characterization compared with those for the SV of variable thicknesses. Moreover, it is obtained that the fractional changes of deposited energy within the SVs of different thicknesses present a saturating trend, which can be accelerated by the increment of incident angle, and this evidence would be helpful for deeply comprehending why the implicit inaccuracy of the SEU saturated cross-section happened under the metrics of LET or ion velocity. Ultimately, the dependence of deposited energy on the surface area and thickness is further explored and discussed based on the geometrical property and radial track profile.

Efficacy of Spatial and Temporal RHBD Techniques at Advanced Bulk FinFET Technology Nodes

Single-event (SE) performance of a variety of radiation-hardened by design (RHBD) flip flop (FF) circuits are evaluated at the 7-nm and 5-nm bulk FinFET nodes. For a given RHBD technique, the 5-nm node design has a single-event upset (SEU) cross-section an order of magnitude higher than that at the 7-nm node. Such an increase in SEU cross-section was not seen with scaling of previous nodes. Simulations indicate that the increase in SEU cross-section is due to disproportionate changes in single-event transient pulse-widths and sensitive areas after an ion strike. A figure-of-merit is proposed to quantify the efficacy of a given RHBD technique. RHBD FF designs are evaluated using this metric to show the efficacy of spatial and temporal RHBD techniques at the 7-nm and 5-nm technology nodes at both nominal and reduced supply voltage operations.

A Method of Predicting Muon-Induced SEUs Using Proton Tests and Monte Carlo Simulation

We have proposed a method based on proton accelerating test and Monte Carlo simulation to predict single event upsets (SEUs) caused by positive muons. The proton energy is mapped to the muon one by making their Bragg peaks overlapped at the sensitive volume (SV) in a device. The fluxes of incident particles reaching the SV are different between protons and positive muons due to the energy straggling in the device. This difference is considered in our newly proposed method and the proton SEU cross section is converted to the corresponding muon SEU cross section. We have demonstrated the feasibility of this method using the experimental data of muon-induced SEUs and the simulation result of proton-induced ones for a 65-nm bulk SRAM. The feasibility test showed good agreement between the experimental muon SEU cross sections and the muon SEU ones predicted by the proton simulation.

An Analysis of the Significance of the 14N(n, p) 14C Reaction for Single-Event Upsets Induced by Thermal Neutrons in SRAMs

The thermal neutron threat to the reliability of electronic devices caused by <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> B capture is a recognized issue that prompted changes in the manufacturing process of electronic devices with the aim of limiting as much as possible the presence of this isotope nearby device sensitive volumes. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N can also capture thermal neutrons and release low-energy protons (through the <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N(n,p) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> C reaction) that have high enough linear energy transfer to cause single-event upsets (SEU). Typically, nitrogen is used in thin barrier layers made of TaN or TiN or even as insulator in the form of Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> . Numerical simulations on sensitive volumes calibrated on proton and ion experimental data and with an accurate description of the metallization layer on top of the sensitive region show that the presence of nitrogen in these thin barrier layers can be enough to justify the experimentally observed thermal neutron SEU cross section for a static random access memory sensitive to low-energy protons. Nevertheless, the expected SEU cross section from thermal neutrons is usually a few orders of magnitude lower than that of high-energy particles, therefore, not representing an important threat in atmospheric applications. At the same time, for high-energy accelerators, the contribution to the total soft error rate could become substantial, though easy to handle by margins.

SEU Performance of RHBD Flip-Flops Using Guard Gates at 22-nm FDSOI Technology Node

Because of the isolation of transistors, fully-depleted silicon-on-insulator (FDSOI) technology nodes have shown better single-event upset (SEU) resilience compared with bulk technology nodes. Additional radiation-hardening-by-design (RHBD) techniques can further improve the SEU performance. In this paper, SEU performance of multiple RHBD flip-flop (FF) designs using the guard-gate circuit at a 22-nm FDSOI technology is presented, including a conventional FF, a guard-gate (GG) FF, a dual-feedback-recovery (DFR) FF, and a GG-Dual-Interconnected Storage Cell (DICE) FF. Irradiation results showed significant reductions in SEU cross-sections for hardened designs compared to the conventional design. Specifically, the conventional GG design demonstrates more than 100X improvement over a conventional FF design, while DFR and GG-DICE designs showed no upsets for all test conditions. Further analysis was carried out to explain the SEU performance differences between the GG and DFR FF designs, and it is noted that proper layout arrangement is critical for achieving ideal SEU mitigation in this FDSOI technology node.

Measurements of radiation effects in an antifuse FPGA

This paper presents the irradiation and the measurement analysis for a commercial antifuse Field Programmable Gate Array (FPGA) from Microsemi’s Axcelerator family, part number AX250. Following proton and X-ray beam irradiation, at very high dose rate above 1krad/s, the total ionizing dose (TID) first effects were visible around 260 krad (SiO 2), and this threshold value increases at lower radiation dose rates. We expect for most space and accelerator applications that this value will be at least several Mrads, or even that the FPGA might never reach this threshold. At very high radiation dose rates, TID-induced leakage currents were observed in the device. FPGA data were recorded continuously for more than 100 h after each irradiation with a fully operating FPGA. Quantitatively, the room-temperature annealing of the radiation-induced defects leads to a fast decrease of the device leakage current by a factor of 7 in the first 100 h after irradiation. The last measurements done after three months place the currents to within 30% to 70 % relative to the before-irradiation values in case of two tested FPGA. Several firmware configurations were used to test different logic resources and to measure single event upsets (SEUs). An upper limit of SEU logic cross-section was found to be (2.56 ± 0.51) ⋅ 10−13 cm 2/FPGA for dose rates around 1krad/s. SEU cross-section values for RAM blocks have on average a value of (3.72 ± 0.8) ⋅ 10−14 cm 2/bit. The complete list of results is given and the effects are extrapolated to a high-energy physics experiment environment — LHCb RICH at CERN.

Neutron-Irradiation Testing of FPGA-Embedded Hadron Fluence Sensors

Hadron fluence monitors based on static random access memories (SRAMs) are being used at CERN and have been proposed for proton therapy facilities. Some of the limitations of the state of the art are related to the usage of separate components for sensing upsets and for reading them out, as these increase the power consumption, the board complexity and its size. Moreover, in some cases, due to radiation-tolerance requirements, the readout logic is fixed and it cannot be updated once the system has been implemented. In this work, we show how to overcome the mentioned limitations by using an SRAM-based field programmable gate array (FPGA) for implementing both the sensitive element (the configuration SRAM) and the readout logic (the firmware in the fabric). In fact, we describe the implementation of a compact, reprogrammable, low-power, actively self-reading hadron fluence sensor realized by means of a Xilinx Artix-7 FPGA. Moreover, we present the customized radiation-hardening-by-design techniques adopted for the readout logic. We irradiated two sensor prototypes at the Jožef Stefan Institute’s TRIGA Mark II research reactor, under different neutron spectra and flux conditions. We discuss our results, which include the measurements of the radiation tolerance, the single event upset cross section of the configuration SRAM, the sensitivity to thermal neutrons, and the failure cross section of the readout logic.

Single-Event Upset Cross-Section Trends for D-FFs at the 5- and 7-nm Bulk FinFET Technology Nodes

At each advanced technology node, it is crucial to characterize and understand the mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm bulk FinFET node had resulted in a decrease in Single-Event Upset (SEU) cross-section at each node. However, this trend unexpectedly reversed for scaling from the 7-nm bulk FinFET node to the 5-nm bulk FinFET node. Experimental results show that the SEU cross-sections for D-FF designs at the 5-nm node are greater than that at the 7-nm for the whole range of particle LET values tested. 3D Technology Computer Aided Design (TCAD) and circuit-level simulations show that the increase in single-event (SE) cross-section with scaling to the 5-nm node is due to interactions between changes in drive current and nodal capacitances. The relative changes in these parameters increased single-event transient (SET) pulse-widths and decreased feedback-loop delays, resulting in an increase in SE cross-sections for the 5-nm node. In addition, the effects of threshold voltage and supply voltage on SEU cross-section for both the 5-nm node and 7-nm node are investigated. The SEU cross-section for the D-FF designs at the 5-nm node shows a stronger dependence on both threshold voltage and supply voltage than that for the 7-nm node. As critical charge decreases with scaling, small differences in critical charge become more significant and manifest as large changes in SEU cross-section, as observed for the 5-nm node. Designers will need to be particularly careful in assessing the overall SE susceptibility of systems developed using the 5-nm bulk FinFET node, particularly when different threshold voltage options and supply voltages are used across the IC.

Analysis of Single-Event Upsets and Transients in 22 nm Fully Depleted Silicon-On-Insulator Logic

In this work, single-event upset (SEU) and single-event transient (SET) responses of digital logic in a planar 22nm fully-depleted conventional-well silicon-on-insulator (FD-SOI) technology under various test conditions are presented. The D-flip-flop (DFF) shift registers used for the single-event upset experiments are more sensitive to upsets when data is dynamically loaded in during irradiation rather than statically stored beforehand, but the clock rate used to load the data does not affect the upset cross sections in any significant way. The digital pattern loaded also affects the upset cross sections, but which cross section is greater between patterns of all “1s” and all “0s” is observed to be opposite for dynamic and static tests. A key capability of the technology studied in this work is the ability to apply biases to the back gates of transistors to alter threshold voltage. For conventional-well designs, as in this work, reverse body bias can be applied, increasing the threshold voltage and decreasing leakage current. Analyzing the effects of applying a back-gate bias on single-event upset cross section reveals no clear trend for single-event upset cross sections in the D-flip-flop shift registers but applying back-gate bias decreased the single-event transient cross sections measured from an inverter chain by as much as an order of magnitude. Supplementary SPICE-level simulations suggest that the drastic decrease in single-event transient cross section results from attenuation in the inverter chain. The presented experimental and simulation results indicate relatively small single-event cross sections compared to other technologies reported in literature.

Threshold and Characteristic LETs in SRAM SEU Cross Section Curves

Characterizing the sensitivity of a static random access memory (SRAM) to single-event upset (SEU) is an essential task for assuring its soft-error reliability. However, this task often imposes a burden because it usually requires many cycles of accelerator-based irradiation tests. A model recently proposed is a very simple exponential-type equation but has strong potential to reduce the burden because of its capability to predict SEU cross sections in various conditions. The aim of the present study is to revisit the model in terms of threshold parameters called threshold linear energy transfer (LET) and critical charge. Although these threshold parameters are widely used as key parameters that describe whether an SEU occurs or not, they are not seen in the model. This article explores such missing threshold parameters, suggesting that they successfully appear by introducing a factor of five to the original expression.

Proton Direct Ionization Upsets at Tens of MeV

Experimental mono-energetic proton single-event upset (SEU) cross-sections of a 65 nm low core-voltage static random access memory (SRAM) were found to be exceptionally high not only at low energies (< 3 MeV), but also at energies > 3 MeV and extending up to tens of MeV. The SEU cross-section from 20 MeV protons exceed the 200 MeV proton SEU cross-section by almost a factor of 3. Similarly, mono-energetic neutron cross-sections at 14 MeV are about a factor of 3 lower than the 20 MeV proton cross-section. Thanks to Monte-Carlo (MC) simulations it was determined that this strong enhancement is due to the proton direct ionization process as opposed to the elastic and inelastic scattering processes that dominate the SEU response above 3 MeV in other SRAMs. As shown by means of a detailed energy deposition scoring analysis, however, this does not appear to be caused by the critical charge of the SRAM being lower than the charge resulting from the average proton ionization through the linear energy transfer (LET). On the other hand, this is caused by high-energy δ-rays (> 1 keV) that can deposit their full kinetic energy within the sensitive volume (SV) of a cell despite their range being theoretically much longer than the characteristic size of the SV. Multiple scattering events are responsible for increasing the trajectory path of the δ-rays within the sensitive volume, resulting in a 6 fold increase in the probability of upset with respect to the sole electron ionization.

Efficacy of Transistor Stacking on Flip-Flop SEU Performance at 22-nm FDSOI Node

Fully depleted silicon-on-insulator (FDSOI) technology nodes offer better single-event performance compared with comparable bulk technologies. However, upsets are still possible at nanoscale feature sizes and additional hardening techniques need to be explored. Single-event upset (SEU) performance of multiple flip-flop designs using the stacked-transistor hardening technique at a 22-nm FDSOI technology node is presented in this paper. Irradiation results show significant reductions in SEU cross-sections for stacked-transistor-based hardened designs compared to a conventional design. Alpha particle exposures showed zero upsets for all D-Flip-Flop (DFF) designs tested. When exposed to heavy-ions, the stacked-transistor DFF design showed a 17X improvement over a conventional DFF design at an LET value of 47 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. The stacked-transistor design with the charge-cancelling technique showed upsets when particle LET exceeded 93.8 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg and at a high angle of incidence. The stacked-transistor design with the interleaving technique showed zero upsets for all test conditions.

Influences of well contact on multiple-cell upsets in 28 nm SRAM

In order to study the effects of the feature size reduction and well contact placement on the characterization of topology patterns and the charge collection mechanism of device heavy ion single event multiple upset on a nanometer scale, the heavy ion single event effect experiment on the domestic 28 nm static random-access memory (SRAM) is carried out on the experimental platform of HI-13 heavy ion accelerator in Beijing. Based on the mapping relationship between the logical address and physical address of the device, the experimental data are processed, and the 28 nm SRAM heavy ion single event upset cross section curves, multiple upset percentage, and multiple upset topology patterns are obtained. The results are compared with those of heavy ion single event effect experiments in 65 nm SRAM, showing that under the influences of factors such as feature size reduction and lower operating voltage, the heavy ion single event upset threshold and the bit upset saturation cross section of 28 nm SRAM decrease significantly. In the direction perpendicular to the well, owing to the reduced 28 nm SRAM feature size, even if the single nucleon energy of the incident high LET (linear energy transfer) heavy ion is low, its deposited charge is sufficient to affect the three SRAM cells across the well direction due to the combined effect of ion track coverage, well potential modulation caused by the parasitic bipolar amplification effect and carrier diffusion, resulting in the fact that the 28 nm SRAM topology pattern has a shape of &lt;i&gt;n&lt;/i&gt; rows × 3 columns, which poses new challenges and requirements for the anti-radiation hardened technology with scrubbing and EDAC (error detection and correction). Owing to the global well contact deployment, the charge deposited by the incident ions in the well far away from the well contact is difficult to discharge quickly, and the parasitic bipolar amplification effect lasts longer. The charge sharing competition between two p-channel metal oxide semiconductor in SRAM cell causes the single event upset recovery, which is the fundamental reason why the discontinuity of multiple upset topology pattern appears in 28 nm SRAM. This study provides a new anti-radiation hardened idea for suppressing the single event upset by using the parasitic bipolar amplification in the future.

Direct measurement of an energy-dependent single-event-upset cross-section with time-of-flight method at CSNS

To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset (SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with the Back-n white neutron source at the China Spallation Neutron Source. The measured cross section is consistent with the soft error data from the manufacturer and the result suggests that the threshold energy of the SEU is about 0.5 MeV, which confirms the statement in Iwashita’s report that the threshold energy for neutron soft error is much below that of the (n, α) cross-section of silicon. In addition, an index of the effective neutron energy is suggested to characterize the similarity between a spallation neutron beam and the standard atmospheric neutron environment.

Mechanisms and shielding characteristics of alpha particle-induced soft errors in 28 and 40 nm configuration memories of SRAM-based FPGAs

The Am-241 radioactive source is used to investigate the mechanism of alpha particle-induced soft errors in configuration memories of SRAM-based FPGAs. Aluminum foils with different thicknesses are inserted between the Am-241 source and the devices under test (DUTs) to investigate shielding characteristics. The results show that the per-bit single event upset (SEU) cross section of the 28 nm device is 14.4 % smaller than that of the 40 nm device. The SEU cross section of the devices increases as the operating voltage decreases. After inserting an aluminum foil, a significant drop in the SEU cross section is observed. For an aluminum foil thickness of 18 μm, the SEU cross section of the 28 nm device drops to zero. The particle transport and SEU generation processes are investigated using Monte Carlo simulations. For a 6 μm aluminum foil thickness, the deposited energy (Ed) at the peak of the Ed spectrum is larger than that without the aluminum foil. If the critical charge of the DUT is lower than 1.33 fC, the SEU cross section will decrease, as the thickness of the aluminum foil increases. However, if the critical charge is higher than 1.33 fC, the introduction of the aluminum foil may lead to an increase in the SEU cross section. This is because that, although the aluminum foil slows down the alpha particles and shields part of low-energy alpha particles, the linear energy transfer (LET) value of the alpha particles reaching the sensitive volume increases.

Single event tolerance of x-ray silicon-on-insulator pixel sensors

We evaluate the single event tolerance of the x-ray silicon-on-insulator (SOI) pixel sensor named XRPIX, developed for the future x-ray astronomical satellite FORCE. In this work, we measure the cross-section of single event upset (SEU) of the shift register on XRPIX by irradiating heavy ion beams with linear energy transfer (LET) ranging from 0.022 to 68 MeV / ( mg/cm2 ) . From the SEU cross-section curve, the saturation cross-section and threshold LET are successfully obtained to be 3.4−0.9+2.9×10−10 cm2/bit and 7.3−3.5+1.9 MeV/(mg/cm2), respectively. Using these values, the SEU rate in orbit is estimated to be ≲ 0.1 event / year primarily due to the secondary particles induced by cosmic-ray protons. This SEU rate of the shift register on XRPIX is negligible in the FORCE orbit.

The Effects of Total Ionizing Dose on the SEU Cross-Section of SOI SRAMs

The total ionizing dose (TID) effects on single-event upset (SEU) hardness are investigated for two silicon-on-insulator (SOI) static random access memories (SRAMs) with different layout structures in this paper. The contrary changing trends of TID on SEU sensitivity for 6T and 7T SOI SRAMs are observed in our experiment. After 800 krad(Si) irradiation, the SEU cross-sections of 6T SRAMs increases by 15%, while 7T SRAMs decreases by 60%. Experimental results show that the SEU cross-sections are not only affected by TID irradiation, but also strongly correlate with the layout structure of the memory cells. Theoretical analysis shows that the decrease of SEU cross-section of 7T SRAM is caused by a raised OFF-state equivalent resistance of the delay transistor N5 after TID exposure, which is because the radiation-induced charges are trapped in the shallow trench, and isolation oxide (STI) and buried oxide (BOX) enhance the carrier scattering rate of delay transistor N5.

Back gate impact on SEU characterization of a Double SOI 4k-bit SRAM

In this paper, heavy-ion single-event effects studies are investigated on a 0.2 μm Double silicon-on-insulator (DSOI) 4k bit Static Random Access Memory (SRAM). The back gate bias is used to adjust the single event upset (SEU) rate of the SRAM circuit. Experimental results show that applying a -5 V bias to the back gate of nMOSFETs can reduce the SEU cross section by 31 % ~ 62 %, and the SEU rate by 61 %. While applying to the back gate of both nMOSFETs and pMOSFETs a 5 V bias can increase the SEU cross section by 43 % ~ 298 %, and the SEU rate by 3 orders of magnitude. The SEU rate is calculated using OMERE software under the GEO orbit with a 3 mm aluminum shielding condition. To further analyze the cause of this phenomenon, TCAD simulation and DSOI MOSFETs test were introduced in this paper. Results show that applying a negative bias to the back gate of nMOSFETs will reduce the single particle transient (SET) and increase the threshold voltage of nMOSFETs, which makes the SRAM cell more tolerant to SEU; while applying a positive bias to the back gate of pMOSFETs will decrease the drive current of pMOSFETs, which makes the SRAM cell more sensitive to SEU.