Single-event Gate Rupture Research Articles

Refined Analysis of Leakage Current in SiC Power Metal Oxide Semiconductor Field Effect Transistors after Heavy Ion Irradiation

A leakage current is the most critical parameter to characterize heavy ion radiation damage in SiC MOSFETs. An accurate and refined analysis of the source and generation process of a leakage current is the key to revealing the failure mechanism. Therefore, this article finely tests the online and post-irradiation leakage changes and leakage pathways of SiC MOSFETs caused by heavy ion irradiation, analyzes the damaged location of the device in reverse, and discusses the mechanism of leakage generation. The experimental results further confirm that an increase in the leakage current of a device during heavy ion irradiation is positively correlated with the applied voltage of the drain, but the leakage path is not direct from the drain to the source. The experimental analysis of the source of the leakage current of the device after irradiation indicates that there is also a leakage current path between the device gate and source. The research results suggest that the experimental sample is more prone to a single-event gate rupture effect under this heavy ion radiation condition. The gate breakdown mainly occurs in the gate oxide layer at the neck region. This research can provide a theoretical basis for the radiation resistance reinforcement of SiC power devices.

Simulation study on single-event burnout in field-plated Ga2O3 MOSFETs

This paper presents the 2-D numerical simulation results of the heavy-ion induced single-event burnout (SEB) and single event gate rupture (SEGR) in the depletion-mode gallium-oxide (Ga2O3) field-plated metal-oxide-semiconductor field-effect transistors (FP-MOSFETs). The employed simulation physics models and material parameters were validated by the basic electrical characteristics in experiments. The SEB sensitive region was proven to be from the gate edge to the drain edge of the structure. The SEB failure could result from the large number of mobile holes that diffused into the strong electric field to form a very large joule heat power to induce thermal failure. Meanwhile, the SEGR sensitive region overlapped with that of the SEB. The accumulated at the gate channel interface could produce a high-density hole pool that formed a large positive potential to induce an SEGR. Based on the simulations, a catastrophic SEB was triggered at a drain voltage of around 350 V, which was 46.4 % of breakdown voltage. Besides, a severe leakage current degradation could be estimated at about 175 V. However, for the SEGR performance, an SEGR could be triggered even at 0 V. Finally, the influences of the field plate extension length on SEB and SEGR were investigated that the SEB sensitive region and maximum electric field during SEGR could be both improved.

Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure

Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region has been damaged. The SEGR-hardened termination with multiple implantation regions is proposed and simulated using the Sentaurus TCAD. The multiple implantation regions are introduced, leading to an increase in the distance between the gate oxide and the hole accumulation region, as well as a decrease in the resistivity of the hole conductive path. This approach is effective in reducing the electric field of the gate oxide to below the calculated critical field, and results in a lower electric field than the conventional termination.

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose (TID) and single event gate rupture (SEGR) in SiC power metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Study of heavy ion induced single event gate rupture effect in SiC MOSFETs

Single Event Gate Rupture (SEGR) is one of the most severe problems that SiC MOSFETs experience in the space radiation environment. The influence of drain bias (V DS) and gate bias (V GS) on SEGR was explored in this work using the fluctuation of leakage current when the device was irradiated at various biases. The source of leakage current is isolated and determined through testing, and the influence mechanisms of V GS and V DS effects on SEGR are further explored using TCAD simulation. The investigation demonstrates that while the drain bias can indirectly enhance the potential of SiC-side oxide, the gate bias can directly alter the potential of metal-side oxide during heavy ion irradiation. When gate bias and drain bias are combined, a strong electric field is generated in the gate oxide, resulting in SEGR in SiC MOSFETs. In addition to single event burnout, the SEGR effect is a significant issue for SiC MOSFETs due to their high susceptibility to heavy ion irradiation.

Simulation Study of Single-Event Effects for the 4H-SiC VDMOSFET With Ultralow On-Resistance

Silicon carbide (SiC) vertical-diffused metal oxide field transistor (VDMOSFET) is an important power device for aerospace application. However, it is sensitive to heavy particles radiation in space which can cause catastrophic single-event effects (SEEs). In this article, a method of SEE hardening at a high linear energy transfer (LET) value range is studied to the 1.2 kV-rated SiC VDMOSFET by the 2-D numerical simulator SILVACO TCAD. Simulation results illustrate that, compared with the VDMOSFET which only has four buffer (FB-VDMOSFET) layers, the improved MOSFET could increase the abilities of single-event burnout (SEB) and the single-event gate rupture (SEGR) of the device effectively. At the same time, the proposed MOSFET has the lower specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on, sp}}$ </tex-math></inline-formula> ) at room temperature. As a result, the gate oxide of the FB-VDMOSFET has reached 7.5 MV/cm and the maximum temperature reached 2480 K at a voltage of 600 V and an LET value of 0.5 pC/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> . However, the maximum temperature of the improved VDMOSFET is 2150 K when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm {DS}}$ </tex-math></inline-formula> = 950 V.

A 15 V-Tolerant and Radiation-Hardened MOSFET Driver With Positive and Negative References

Radiation-hardened and high-voltage power circuits are key components in aerospace applications. However, when working at high voltages, the effects of the total ionizing dose (TID) and the single event limit the application of power driving circuits in a radiation environment. A 15 V-tolerant radiation-hardened MOSFET driver was designed. The circuit architecture, which is based on positive and negative references, can reduce the gate source voltage of the transistors to less than 5&#x00A0;V, allowing the selection of thin-gate oxide high-voltage transistors. On this basis, adopting enclosed layout transistor (ELT) N-channel metal oxide semiconductor (NMOS) transistors helps the driver to obtain a good resilience to TID hardness. Additionally, this work optimized the layout of high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS) transistors in the driver to effectively improve the single-event burnout (SEB) threshold. Three chips with different N-type drift region lengths were designed and fabricated in a 0.35&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> BCD process. The test results showed that the TID hardening capability of these chips with ZENER references and ELT NMOS transistors all exceeded 100 krad (Si). In addition, this driver was tested under heavy ion irradiation with linear energy transfer (LET) exceeding 75 MeV&#x00B7;<inline-formula><tex-math notation="LaTeX">$\dot\mathrm{{c}}{\mathrm{{m}}^{2}}\mathrm{{/mg}}$</tex-math></inline-formula>. The results show that this driver with a 6.6&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> drift region length had no single event latchup (SEL), single event gate rupture (SEGR), or single event burnout (SEB) sensitivity.

Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

This article presents design for a 650-V super-junction (SJ) power metal–oxide–semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

Analysis and Mitigation of Single-Event Gate Rupture in VDMOS With Termination Structure

During heavy-ion experiments, the single-event gate rupture (SEGR) effects can still be observed in the vertical double-diffused power MOSFET (VDMOS) with radiation-hardened cells. Fault analysis demonstrates that the hot spots locate at the termination of the VDMOS. Then, several mitigation solutions for termination structure are discussed comprehensively by means of TCAD simulations. Finally, a combined hardness method with horizontally extending P+ region and adding floating N+ region is proposed. It is effective to reduce the electric field of gate oxide to below the calculated critical field, without additional masks and process steps.

Experimental investigation on the single event gate rupture and hardening of the 600 V trench IGBT

In this paper, a single particle irradiation experiment is performed on the 600 V trench insulated gate bipolar transistor for the first time. The experimental results show that, at the collector voltages of 100 V and 300 V, single event gate rupture occurs in the device under the linear energy transfer of 81.35 MeV cm2/g. The damage occurs in the gate oxide layer near the bottom of the trench gate. The simulation results show that the holes accumulated at the bottom of the trench gate increase the electric field under irradiation, which causes the failure of the gate oxide. Furthermore, the hardening device structure is proposed by increasing the thickness of the bottom gate oxide.

Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.

Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons.

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed.

Single-Event Effects in SiC Double-Trench MOSFETs

Single-event effects (SEEs) in a 650-V state-of-the-art SiC double-trench MOSFET (DT-MOS) are investigated using the Sentaurus TCAD tools. The safe operation areas (SOAs) for single-event burnout (SEB) and single-event gate rupture (SEGR) are extracted when heavy ions with different linear energy transfer (LET) impact the sensitive regions of the device. The results show that the radiation performance of the SiC DT-MOS is poor because of the very low threshold voltages of failures at a high LET range. Moreover, hardening measures, such as introducing a buffer layer and adjusting the mesa width, are discussed to assess their versatility. It is demonstrated that in contrast, the SEGR problem is more severe due to the intrinsic properties of SiC devices. Therefore, it becomes a crucial issue to find ways more suitable for the SiC DT-MOS to avoid gate oxide pre-breakdown, before they could serve as a replacement of Si counterparts in space applications.

Gate Damages Induced in SiC Power MOSFETs During Heavy-Ion Irradiation—Part II

This article presents the results of a 2-D finite element simulation study of the gate damages induced by heavy-ion irradiation in SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The time evolution of the electric field in the gate oxide is studied. Two effects are investigated: the first is associated with the charge deposition in the SiC portion of the MOSFET, with the time evolution studied using the 2-D finite element simulator; the second one results from holes generated during the ion transit, trapped in the gate oxide after the fast electrons have been quickly swept away by the electric field. Two different techniques have been combined for estimating the hole concentration in the gate oxide: the well-known recombination rate was modified to consider the trapped charge yield, as was recently done to better interpret single event gate rupture (SEGR) failure of silicon power MOSFETs. Under ion irradiation test conditions at which the gate damage experimentally starts to be observed, we demonstrate that, because of the ion impact, regardless of the ion linear energy transfer (LET), the peak value of the electric field in the gate oxide becomes practically equal to the oxide breakdown field (~12–15 MV/cm). Moreover, we show that simulations can be used to predict the test conditions at which gate damage starts to appear as a function of LET and the range of heavy ions used in the irradiation experiments.

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

Increased electrification of traditionally hydraulic and pneumatic functions on aircrafts has put power electronics at the heart of modern aviation. Aircraft electrical power systems have traditionally operated at 115 V AC and 28 V DC with a constant speed generator and transformer rectifier units converting jet engine power into electrical power. However, due to the increasing trend towards the More Electric Aircraft (MEA), 270 V DC systems are likely in the future. This calls into question, the power semiconductor device technology that enables the on-board power converters needed for electro-mechanical actuation as well as solid-state circuit breakers for system protection. Silicon IGBTs have been the work-horse of power electronics, but as switching speeds increase due to the need for high frequency operation, the bipolar nature of IGBT tail currents become a limiting factor for improved energy conversion efficiency. A number of unipolar FET technologies, including SiC trench MOSFETs, SiC planar MOSFETs, silicon super-junction MOSFETs and SiC JFETs in cascode with a low voltage Si MOSFET, have become commercialized at around 650 V. However, reliability and robustness, especially against single event burn-out and/or single event gate rupture is critical. This paper experimentally investigates the performance of the listed FET devices under Unclamped Inductive Switching and Bias Temperature Instability/gate oxide stress tests.

Physical Analysis of Damage Sites Introduced by SEGR in Silicon Vertical Power MOSFETs and Implications for Postirradiation Gate-Stress Test

The damage sites introduced by single-event gate rupture (SEGR) in Si vertical power MOSFETs were physically analyzed to clarify their location and structures. It was found that the damage sites were located on the neck region between p-body diffusions as expected, and the gate oxide was replaced by Si to electrically connect the gate poly-Si and Si-substrate at the damage sites. As a result, the complicated electrical properties observed on the damaged device were successfully modeled by assuming an Si spike at the damage site in device simulations. It was also suggested that the postgate-stress test with applied voltage higher than that applied during the SEGR test might have forced additional thermal stress on the damage site and have caused the failure attributable to the postgate-stress test itself.

Updated structure of vertical double-diffused MOSFETs for irradiation hardening against single events

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm2/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.

Single-Event Damage Observed in GaN-on-Si HEMTs for Power Control Applications

The single-event damage observed in AlGaN/GaN high-electron mobility transistors (HEMTs) was investigated. For power control applications, normally off operation is achieved by p-type GaN gate material and its rated drain–source voltage of 600 V. Because of no gate insulator, single-event gate rupture is essentially excluded. Therefore, the HEMTs are expected to exhibit better immunity to heavy ions in comparison with SiC power MOSFETs. In the test results, two types of catastrophic failure modes were observed with different leakage current paths; one failure mode was caused by the introduction of a leakage current path between the drain and Si substrate via the buffer layer. The other was caused by the damage between the drain and source electrodes.

SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs * * Project supported by the National Natural Science Foundation of China (No. 61464002), the Grand Science and Technology Special Project in Guizhou Province of China (No. [2015]6006), and the Ministry of Education Open Foundation for Semiconductor Power Device Reliability (No. 010201).

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture (SEGR) and single event burnout (SEB), which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOSFETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers. Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV·cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.

Radiation and High-Voltage Tolerant Space CAN Driver in Standard Low-Voltage 3.3 V CMOS Technology

The control area network (CAN) wired communication standard is becoming the bus of choice for many space applications. However, the severe −2 to 7 V common-mode and −3 to 16 V failure tolerance requirements of the CAN bus driver have restricted its implementation of commercial high-voltage processes with transistors tolerant to voltages above 16 V. These transistors experience sensitivity to single-event gate rupture (SEGR) and single-event breakdown (SEB) radiation events and have led to the limited diffusion of commercial available CAN transceivers in space applications. This paper demonstrates, for the first time, that a radiation-tolerant CAN driver can also be realized with the radiation-tolerant low-voltage design against radiation effects (DARE) mixed-mode 180-nm CMOS technology. This has been made possible by the development of a specific driver circuit that increases in static and dynamic operations of the technology voltage handling range from 3.3 to 16 V, while maintaining the radiation tolerance. This CAN driver has been manufactured and tested under heavy ion radiation in excess of linear energy transfer (LET) of 60 MeVcm2/mg. Over the CAN common mode and failure tolerance voltage range up to 16 V, this CAN driver has been tested and found to have a high threshold and low cross section to radiation-induced single-electron transients and an absence of single-event latch-up, SEGR, and SEB sensitivity.