Single-event Gate Rupture Research Articles

Long-term reliability degradation of ultrathin dielectric films due to heavy-ion irradiation

High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO/sub 2/-film MOS capacitors show premature breakdown during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. The reliability degradation due to high-energy ion-induced latent defects is explained by a simple percolation model of conduction through SiO/sub 2/ layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. These results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.

A new physics-based model for understanding single-event gate rupture in linear devices

This paper presents a new physics-based model for understanding the basic mechanism of single-event gate rupture (SEGR) in analog devices. This model accounts for the different competing physics mechanisms, such as carrier drift, diffusion, recombination in the drift diffusion, and Poisson's equations, to explain the dependence of SEGR on biasing voltage, cross section, and critical electric field strength. Hence, the model provides a more accurate method of understanding and predicting the breakdown of oxides from heavy-ion strikes.

A study of ion energy and its effects upon an SEGR-hardened stripe-cell MOSFET technology [space-based systems

Experimental observations of an improved single-event gate rupture (SEGR) hardened stripe-cell MOSFET demonstrated that ion beam energy, penetration depth, and strike angle (tilt angle) have a significant influence upon the measured SEGR failure threshold voltage.

An improved stripe-cell SEGR hardened power MOSFET technology

A new single-event gate rupture radiation-hardened power MOSFET is reported. It is based upon a well-established radiation-hardened technology described in 1996. The hexagonal cells used in prior work are replaced with a stripe-cell structure producing demonstrated performance improvements.

Early lethal SEGR failures of VDMOSFETs considering nonuniformity in the rad-hard device distribution

In 1999, Titus et al. studied single-event gate rupture failures of vertical MOSFETs for many parameters where the MOSFET universe was assumed to consist of homogeneous devices. A non-homogeneous universe is now considered. Time-to-failure is studied using Monte Carlo methods. Boundaries are ascribed applying the empirical equation presented by Titus et al.

The electron irradiation effects on silicon gate dioxide used for power MOS devices

The work provides experimental results of high energy electron irradiation effects on silicon dioxide used for power MOS devices. A systematic increase of the threshold voltage has been observed in irradiated IGBT and VDMOS devices processed on Si 〈1 0 0〉 and Si 〈1 1 1〉 , respectively. The threshold voltage shift has been interpreted as a result of the accumulated charge in the gate oxide. Single event gate rupture has been observed and attributed to the recoil ion interaction with the gate SiO 2. The result has been corroborated by reliability stress tests. After electron irradiation, an increase in breakdown voltage appeared on all devices which was attributed to a change in the surface impact ionisation coefficient. The change is most notable in devices processed on Si substrate with 〈1 1 1〉 orientation.

The impact of single event gate rupture in linear devices

A number of analog devices has exhibited permanent single event failure when exposed to heavy ions of LETs 26.6 MeV cm/sup 2//mg or higher. Single event gate rupture (SEGR) was uncovered to be the failure mode in several analog circuits using failure analysis tools and circuit modeling. A new approach to assessing the risk of SEGR for a system design will be presented which strongly depends on angles near normal incident and on the critical electric field where SEGR occurs.

Analysis of SEB and SEGR in super-junction MOSFETs

The electric field distribution in the super-junction power MOSFET is analyzed using analytical modeling and numerical simulations in this paper. The single-event burnout (SEB) and single-event gate rupture (SEGR) phenomena in this device are studied in detail. It is demonstrated that the super-junction device is much less sensitive to SEB and SEGR compared to the standard power MOSFET. The physical mechanism is explained.

Prediction of early lethal SEGR failures of VDMOSFETs for commercial space systems'

Quantitative risk assessments are presented for two radiation-hardened MOSFETs (Harris FSL11A0 and FRL11A0) using an extracted expression, integral flux curves representing different conditions, and experimentally-determined signature curves taken at different ion impact angles. The effectiveness of certain parameters including the selected orbit, spacecraft shielding thickness, drain and gate biases, device hardness, and time of exposure are discussed. Failures are studied using normalized Monte Carlo simulations validated by statistical methods. These validated Monte Carlo simulations are then used to extract and present an extracted expression. The concept of a lethal ion rate is discussed. Single event gate rupture (SEGR) failure thresholds at different ion impact angles are measured and reported on the Harris FSL11A0 and FRL11A0 (radiation-hardened vertical MOSFETs having similar layouts but with different SEGR sensitivities). Integral flux curves are presented for various orbits and conditions. Predictions of very early failures are performed using the extracted expression, the integral flux curves, and the new signature curves. Based upon these predictions, the influence of selected parameters are evaluated.

On the role of energy deposition in triggering SEGR in power MOSFETs

Single event gate rupture (SEGR) was studied using three types of power MOSFET devices with ions having incident linear energy transfers (LETs) in silicon from 26 to 82 MeV/spl middot/cm/sup 2//mg. Results are: (1) consistent with Wrobel's oxide breakdown for V/sub DS/=0 volts (for both normal incidence and angle); and (2) when V/sub GS/=0 volts, energy deposited near the Si/SiO/sub 2/ interface is more important than the energy deposited deeper in the epi.

Single event upset immunity of strontium bismuth tantalate ferroelectric memories

An embedded 1 Kbit nonvolatile (NV) serial memory manufactured with strontium bismuth tantalate (SBT) ferroelectric (FE) technology was shown to be immune to effects of heavy ion irradiation. The memories did not lose any data in the non-volatile mode when exposed to xenon (maximum effective LET of 128 MeV-cm/sup 2//mg and a total fluence of 1.5/spl times/10/sup 7/ ions/cm/sup 2/). The ferroelectric memories also did not exhibit any loss in the ability to rewrite new data into the memory bits, indicating that no significant degradation of the FE dipoles occurred as a result of the heavy ion exposure. The fast read/write times of FE memories also means that single event gate rupture is unlikely to occur in this technology.

Precursor ion damage and angular dependence of single event gate rupture in thin oxides

No correlation was observed between single-event gate rupture (SEGR) and precursor damage by heavy-ion irradiation for 7-nm thermal and nitrided oxides. Precursor ion damage at biases below SEGR threshold for fluence variations over three orders of magnitude had no significant effect on SEGR thresholds. These data support a true single ion model for SEGR. A physical model based on the concept of a conducting pipe is developed that explains the empirical equation for the linear dependence of inverse critical field to rupture with LET. This model also explains the dependence of critical voltage on angle of incidence. As the oxide thickness approaches the diameter of the conducting pipe, the angular dependence of the critical voltage disappears. A model fit to the data suggests a central core diameter of 6 and 8 nm for conducting pipes induced in MOS oxides by Br and Au ions, respectively. The buildup of precursor ion damage in the oxides depends on ion species and bias during irradiation, but is not consistent with the accumulation of total ionizing dose damage. Some 5-nm oxides exhibited the characteristic high leakage current of SEGR; however, most 5-nm devices showed only soft breakdown during heavy ion exposure with electric fields up to 12 MV/cm.

Effect of ion energy upon dielectric breakdown of the capacitor response in vertical power MOSFETs

The effect of ion energy upon the ion-induced dielectric breakdown response of the capacitor response in vertical power metal-oxide semiconductor field effect transistors (MOSFETs) was investigated. The single event gate rupture response was experimentally determined using mono-energetic ion beams of copper, niobium, and gold. Irradiations were conducted using an ion species tuned to different energies, producing a range of linear energy transfer (LET) values for that ion. Numerous MOSFETs were characterized to identify the onset of ion-induced dielectric breakdown. These data along with previously taken data demonstrated that the ion-induced dielectric breakdown cannot be adequately described in terms of LET, but is better described in terms of atomic number (Z). Based upon these observations, a new semi-empirical expression is presented describing the critical ion-induced breakdown response in terms of Z instead of LET. This expression is shown to be a better single event gate rupture model of the capacitor response.

Single event gate rupture in thin gate oxides

The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for gate oxides from 6 to 18 nm. Capacitor data are compared to SEGR data from full integrated circuits. A 1/E/sub CR/ dependence is found for critical field to rupture as a function of ion linear energy transfer (LET), consistent with earlier work for power MOSFETS with oxide thicknesses from 30 to 150 nm. More importantly, critical field to rupture increases with decreasing oxide thickness, consistent with increasing oxide breakdown field prior to heavy-ion exposure. This suggests that SEGR need not be a limiting factor as future technologies scale into the deep submicron region. However, there is a great deal of uncertainty in how voltage may scale with decreasing oxide thickness, and SEGR may continue to be a concern for devices that operate at electric fields significantly higher than 5 MV/cm.

SEGR and SEB in n-channel power MOSFETs

For particular bias conditions, it is shown that a device can fail due to either single-event gate rupture (SEGR) or to single-event burnout (SEB). The likelihood of triggering SEGR is shown to be dependent on the ion impact position. Hardening techniques are suggested.

Influence of ion beam energy on SEGR failure thresholds of vertical power MOSFETs

For the first time, experimental observations and numerical simulations show that the impact energy of the test ion influences the single-event gate rupture (SEGR) failure thresholds of vertical power MOSFETs. Current testing methodology may produce false hardness assurance.

SEGR: A unique failure mode for power MOSFETs in spacecraft

Power MOSFETs are vulnerable to catastrophic single-event phenomena when exposed to the radiation environment of space. In particular, single-event-gate-rupture (SEGR) is a failure mechanism unique to DMOS power transistors caused by the passage of a heavy ion through the neck region of the device and the subsequent transient electric field across the gate oxide. This paper will describe the failure mode, present supporting experimental data, and demonstrate an effective simulation tool for predicting gate rupture.

Experimental evidence of the temperature and angular dependence in SEGR [power MOSFET

The temperature and angular dependence of Single-Event Gate Rupture (SEGR) experiments, conducted on power DMOS transistors, show that a normal incident angle favors SEGR and elevated temperature is insignificant. Both the oxide and substrate response play a major role in determining the SEGR sensitivity.

Experimental studies of single-event gate rupture and burnout in vertical power MOSFETs

Numerous studies have revealed that vertical power MOSFETs are susceptible to single-event burnout (SEB) and single-event gate rupture (SEGR), resulting in degraded performance or even catastrophic failure when operated in a cosmic-ray environment like space. This paper summarizes many of those experimental studies and examines the problems, test methodologies, and experimental results. Previously unavailable information on SEGR is also provided.

Single-event effect ground test issues

Ground-based single event effect (SEE) testing of microcircuits permits characterization of device susceptibility to various radiation induced disturbances, including: (1) single event upset (SEU) and single event latchup (SEL) in digital microcircuits; (2) single event gate rupture (SEGR), and single event burnout (SEB) in power transistors; and (3) bit errors in photonic devices. These characterizations can then be used to generate predictions of device performance in the space radiation environment. This paper provides a general overview of ground-based SEE testing and examines in critical depth several underlying conceptual constructs relevant to the conduct of such tests and to the proper interpretation of results. These more traditional issues are contrasted with emerging concerns related to the testing of modern, advanced microcircuits.