Single Error Detection Research Articles

High-speed binary coded decimal digit multipliers with multiple error detection

Decimal arithmetic in the form of binary coded decimal (BCD) numbers is preferred in many financial, commercial and scientific applications. BCD multipliers are introduced as a key hardware unit to support both integer and floating-point decimal arithmetic operations. However, due to the increasing sensitivity of VLSI-based digital designs to the environmental effects, BCD multipliers are also prone to faults and errors similar to other arithmetic circuits. In addition, multiple error occurrence is possible in current digital systems especially in space applications which motivates to reach multiple error detection/correction in addition to single errors. In this paper, digit-by-digit BCD multipliers are introduced capable of multiple error detection with low delay overheads. To show the effectiveness of the proposed combined method, a 4-digit BCD multiplier is presented. Experimental results based on analysis and error injection-based simulations show that in addition to 100% single error detection, multiple errors can be detected with at least 99.6% probability in the 4-digit BCD multiplier as the implemented architecture.

Single-Error Detection and Correction for Duplication and Substitution Channels

Motivated by mutation processes occurring in in-vivo DNA-storage applications, a channel that mutates stored strings by duplicating substrings as well as substituting symbols is studied. Two models of such a channel are considered: one in which the substitutions occur only within the duplicated substrings, and one in which the location of substitutions is unrestricted. Both error-detecting and error-correcting codes are constructed, which can handle correctly any number of tandem duplications of a fixed length k , and at most a single substitution occurring at any time during the mutation process.

A SINGLE BIT ERROR DETECTION AND CORRECTION BASED ON THEMRC AND THE MP TECHNIQUES IN RRNS ARCHITECTURE

This paper presents some results on single error detection and correction based on the Redundant Residue Number System (RRNS).The proposed technique utilizes the Mixed Radix Conversion (MRC) and the Modulus Projection (MP) algorithms that significantly simplifies the error correction process for integers. The MP considerably reduces the computational steps and hardware architecture and further improve the processing speed. This results in a considerable improvement in the speed by and tends to require about less hardware resources in the proposed scheme when compared with the existing scheme used in this work. The proposed scheme is built on simple adders in the design of the architecture which saw a considerable improvement in both area and speed in as compared to the work by Yangyang et. al [6] which used ROMs and latches for the design of their architecture.

Algorithm for creating a digital signature with error detection and correction

This paper proposes an algorithm that creates a digital signature in a nonpositional polynomial notation and forms three surplus residues modulo one extension polynomial base number. Such a signature allows for single-error detection and correction (which is shown to be a unique procedure) and multiple error detection. A formula of cryptographic security is obtained for such a digital signature.

Multiple Error Detection in DNA Self-Assembly Using Coded Tiles

This brief deals with error detection in deoxyribonucleic acid self-assembly; coding and mapping functions are utilized to assess a correct (error-free) attachment of a tile to a site in the growth process. The proposed approach utilizes the coding/mapping features of the bonds in the tile set by utilizing single and multiple (combined) properties. Properties are combined through an iterative process that considers the aggregate of the intended pattern through coding of the bonds. As a widely used pattern and instantiation of this process, the Sierpinski Triangle self-assembly is analyzed in detail. The properties proposed for the Sierpinski Triangle allow extending single-error detection to the scenario of multiple clustered errors.

Critical Limitation in Use of τ Test for Gross Error Detection

In the computation of a geodetic network, it is well known that the least-squares adjustment may not be the ideal solution when gross errors appear. In general there are two fundamental approaches to determining gross errors: the application of the detection tests (Baarda’s data snooping, Pope’s τ test, etc.) over the least-squares solution, and the use of robust estimation methods. It has been shown that in the case of more than one gross error, these detection tests become inefficient. Moreover, even for the case of single error detection, these tests may be questionable. Hence, data snooping relies on a good a priori precision estimation, and, regarding Pope’s τ test, it is the purpose of this paper to analyze the limitations in its use with correlated observations, even for a single gross error detection. Conclusions will be drawn by means of a generalization of a result mentioned in Pope’s work (originally restricted to the case of uncorrelated data) and then applied in an example.

Runlength limited codes for single error-detection and single error-correction with mixed type errors

Runlength limited (RLL) codes are used in magnetic recording. The error patterns that occur with peak detection magnetic recording systems when using a runlength-limited code consist of both symmetric errors and shift errors. We refer to shift errors and symmetric errors collectively as mixed type errors. A method of providing error control for mixed type errors that occur in a runlength limited code comprised of (d, k) constrained sequences is examined. The coding scheme is to choose parity blocks to insert in the constrained information sequence. The parity blocks are chosen to satisfy the constraints and to provide some error control. The cases of single error-detection and single error-correction are investigated, where the single error is allowed to be a shift error or a symmetric error. Bounds are discussed on the possible lengths for the parity blocks. It is shown that the single error-detection codes are the best possible in terms of the length of the parity blocks.

Application of byte error detecting codes to the design of self-checking circuits

In this paper, we discuss the application of byte error detecting codes to the design of self-checking circuits for the single stuck-at fault model. We discuss strongly fault-secure realization of a given Boolean function using byte error detecting codes. Even though parity is the most efficient separable code for the detection of single errors, we show that the use of a byte error detecting code can lead to lower cost of self-checking realization of a given function as compared to its self-checking realization using the parity code. We also present a method for the design of totally self-checking checkers for byte error detecting codes. Experimental results obtained for various test circuits are also discussed.

On concurrent multiple error diagnosability in linear analog circuits using continuous checksum

Although most of the work done in fault tolerance is in the digital field, it is widely understood that error detection and correction capability in analog circuits has the same importance as in digital circuits. The technique proposed by Abhijit Chatterjee can realize concurrent single error detection and correction in linear analog circuits well. Based on his work, this paper addresses concurrent multiple error detection and correction in linear analog systems, which is known to be a difficult and unsolved problem. We prove that the concurrent error diagnosis scheme using continuous checksum can not be extended to the case of multiple errors under the assumption that the checker and the functional block will not fail simultaneously, though people are still attempting to make such an extension. © 1998 John Wiley & Sons, Ltd.

On concurrent multiple error diagnosability in linear analog circuits using continuous checksum

Although most of the work done in fault tolerance is in the digital field, it is widely understood that error detection and correction capability in analog circuits has the same importance as in digital circuits. The technique proposed by Abhijit Chatterjee can realize concurrent single error detection and correction in linear analog circuits well. Based on his work, this paper addresses concurrent multiple error detection and correction in linear analog systems, which is known to be a difficult and unsolved problem. We prove that the concurrent error diagnosis scheme using continuous checksum can not be extended to the case of multiple errors under the assumption that the checker and the functional block will not fail simultaneously, though people are still attempting to make such an extension. © 1998 John Wiley & Sons, Ltd.

Runlength-limited codes for single error detection in the magnetic recording channel

An arithmetic function that assigns the value 0, 1, or 2 to each binary sequence is introduced. The authors call this function the error-check value. Two sequences that differ by a single symmetric error or a single shift error are shown to have different error-check values. Runlength-limited codes for detecting single-errors are designed by taking a set of the constrained sequences such that each code sequence has the same error-check value. Systematic runlength-limited codes that detect single errors are constructed, based on the error-check value. It is shown that these systematic runlength-limited codes have the shortest parity length possible for a single error-detecting code. >

Error correction for shaft encoders using M‐sequences

AbstractA method known to be useful in detecting the rotation angle of a device such as motor, is to attach an encoder with M‐sequence to the shaft and to read the angle of the encoder by a sensor. However, in the past, the reading error as the sensor has not been considered in such a shaft encoder using the M‐sequence. This paper proposes a method for error detection and correction. When a reading error is produced in the symbol read by the sensor, it is detected and corrected based on the linear recurrence relation of the M‐sequence. For some given requirements for the measurement accuracy, the number of symbols needed for single error detection and correction is investigated.

Introduction to redundancy coding

An introduction to redundancy encoding as used in digital data communications is described. The need for redundancy is first addressed, followed by a discussion of the binary symmetric channel, burst noise channels, and the use of interleaving to randomize burst errors. The concept of redundancy is presented next, showing how it is used to supply the highest possible degree of error detection or how it can be applied to provide for the detection and correction of a lesser number of errors. The use of some codes to correct some errors and also to detect, but not correct, additional errors is discussed. The properties of block codes are developed beginning with repetition codes then covering single-parity check codes, Hamming (single-error detection) codes, and Bose-Chadhuri-Hocquenghem (BCH)codes. The basic properties and structures of these codes are emphasized with examples of implementation procedures for both encoding and decoding.

Efficient codes for single error detection and partial single error correction

Coding schemes are proposed for error control in systems where individual blocks of information are organised as two sub-blocks each requiring a different degree of error control. The codes described guarantee single error correction in one sub-block and provide single error detection and partial single error correction in the other. The main advantages are savings in redundancy and ability to use standard encoding/decoding procedures.

Information Rates and Errors Using Decision Feedback

Comparison is made between one-way communication links using binary block codes and a similar link with decision feedback. The known reduction in word error probability is shown. Earlier papers consider only the encoding entropy rate. In this paper the equivocation and rate are computed for single-error detection and single-error correction double-error detection codes with and without feedback.

Coding for Multiple Asymmetric Errors in One Channel of a Multichannel System

An efficient error correction code for correcting errors of one kind in an arbitrary N-character message is discussed. The coded check character is obtained by summing the weighted coded characters (columns of binary digits where each binary digit assumes a unique weight) within an entire record modulo a prime integer. This check character is then added to the record before transmission over a channel (e.g., magnetic tape). A single parity check is appended to each character of the record to make possible single error detection per character. The received message, perturbed by noise in a constant position or single track, is decoded by again adding up the received information plus check characters in a modulo p counter. Error location is achieved by solving for x in the expression ax mod p, when a, the number of parity checks that failed, and ax mod p, the contents of a mod p counter, are known. This type of residue check may be employed to indicate which track is in error. Thus, error correction can be performed on the characters containig parity check failures.

A 4-megacycle 24-bit checked binary adder

Recently developed large computers use multiple memory units and buffering between memory and processing to achieve a computation rate higher than the memory rate. In such cases computer speed is limited by the basic adders employed. Because these adders represent a small fraction of the total machine cost, it is economical to use the fastest parallel design available. Checking, if provided, should be accomplished in such a way that the add-cycle time is not increased. This implies parallel rather than serial operation of adder and checking logic. In this paper, the logical design of a 24-bit binary adder developed for the IBM (International Business Machines Corporation) Stretch computer project is described. Direct-coupled type logic is used and high performance is achieved by means of a parallel design employing fast switching devices. Checking employs a combination of parity and duplicate-carry logic for single-error detection.