A 4-megacycle 24-bit checked binary adder

Abstract

Recently developed large computers use multiple memory units and buffering between memory and processing to achieve a computation rate higher than the memory rate. In such cases computer speed is limited by the basic adders employed. Because these adders represent a small fraction of the total machine cost, it is economical to use the fastest parallel design available. Checking, if provided, should be accomplished in such a way that the add-cycle time is not increased. This implies parallel rather than serial operation of adder and checking logic. In this paper, the logical design of a 24-bit binary adder developed for the IBM (International Business Machines Corporation) Stretch computer project is described. Direct-coupled type logic is used and high performance is achieved by means of a parallel design employing fast switching devices. Checking employs a combination of parity and duplicate-carry logic for single-error detection.