Single Error Correction Codes Research Articles

Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead.

INTEGER SINGLE-ERROR-CORRECTING CODES AS AN ALTERNATIVE TO THE INTERNET CHECKSUM

The paper considers the possibility of using integer single-error-correcting (SEC) codes instead of the Internet checksum (IC). It is shown that such a replacement can be easily carried out, since the integer SEC codes are a generalization of the IC.

On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.

Modified single error correction orthogonal Latin square scheme to reduce parity check bits

Single-error correction (SEC) codes play a critical role in ensuring cache reliability. In ultra-high-speed caches, decoding delay is a key element to consider when selecting an SEC code. Single error correction orthogonal Latin square (SEC OLS) codes have the fastest decoding method. However, these codes impose a higher number of parity check bits compared to other SEC codes. These extra parity bits need to be stored with each data word in cache data array, which increased cache overheads. This may limit their adoption only to applications that can handle such overheads. In this paper, a modified SEC OLS coding scheme is proposed to reduce the number of stored parity check bits. Compared to the original SEC OLS codes, the proposed coding scheme reduces 25% and 31.3% of the stored parity bits when implemented to protect 16-bit and 64-bit data words, respectively. The results of FPGA and ASIC simulation and synthesis show that using the modified SEC to protect 16-bit words can be an attractive solution because it saves a significant amount of parities storage area, while running at a speed comparable to the original SEC OLS code. The implementation of the proposed SEC code to protect 64-bit words may still be suitable for area-sensitive cache applications that can cope with the slightly increased decoding delay.

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

Latency optimized clustered error mitigation for multi-level flash memory using product code

Soft errors due to radiation-induced multi-bit upsets (MBUs) are very prominent in the present flash memories built with ultra large scale VLSI technology. Use of multi-level cells in flash memories increase the chance of adjacent MBUs or clustered error. Single bit error detection and correction (EDAC) codes are not enough to mitigate the effect of clustered error due to their small error correction capability. On the other hand, commonly used multi-bit EDAC codes have large overhead, complex decoding circuitry, high error correction latency and are unable to correct large number adjacent erroneous bits. In this paper, we have proposed a product code coined as linear shortened block code based product code (LSBCPC) for mitigation of clustered error in the flash memory devices. LSBCPC utilizes latency optimized scalable shortened block code as the component code and can correct higher number of adjacent erroneous bits in memory devices compared to the other state of the art solutions. The proposed LSBCPC promises better error correction coverage with 28%, 14%, and 13% reduction in terms of redundant bits, 13%, 11%, and 10% reduction in terms of area and 24%, 26%,and 22% reduction in terms of latency in 16 × 16, 32 × 32 and 64 × 64 memory devices respectively compared to the highly cited research work. The performance of the proposed method is validated in terms of redundant bits, error correction coverage, mean error to failure, area consumption, power utilization and decoding latency.

FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application

Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To mitigate these problems, multi-bit adjacent error correcting codes are preferable in SRAM. In this paper, single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are proposed. The performances of the proposed SEC-DED-DAEC codes are observed in terms of area and delay. Theoretical area overhead of proposed codes is at most 49.98% lower compared to the related design. Also the proposed design has around 28.79% lesser critical path delay compared to existing design. The best improvement achieved in terms of number of look-up table (LUT) and delay are 22.69 and 29.98% respectively compared to other existing codes in FPGA platform. The proposed codes can be used in embedded SRAM applications.

Generating nonlinear codes for multi-bit symbol error correction using cellular automata

Error Correcting Codes can be used in cryptography since the security of cryptosystems depends heavily on their resilience against attacks such as fault attacks. In the last three decades, Cellular Automata (CA) have been explored as efficient crypto-primitives as well as to generate error correcting codes. In earlier works, CA are mainly used in bit error correction for Single Error Correcting (SEC) and Double Error Detecting (DED) codes. However, in the practical scenario, when fault is injected by a laser beam or using a clock glitch, multiple bits get infected. The situation thus demands detection/correction of multi-bit errors instead of SEC-DED. In literature, linear CA are used for bit as well as byte error correction. But the CA generating linear codes are of very little use in cryptography as they provide little or no security when used as a component in a cryptosystem. In this paper, linear cellular automata (LCA) with nonlinearity injection at some specific cell positions are used for generating error correcting codes (ECC) which can detect and correct errors in m-bit symbols (m = 8 for a byte). In this paper, we propose coding schemes for single bit as well as multi-bit error correcting codes. For multi-bit error correcting codes, two schemes are proposed. The schemes can easily be extended for generating ECC for different m-bit symbols by simply exploiting m-bit LCA with nonlinearity injection. Moreover, the simple and regular structure of the CA makes the ECC scheme very well suited for VLSI implementation.

Construction of new codes in term‐rank metric

This study investigates codes in the term-rank metric. These codes can be used to correct crisscross errors in a ( M × N ) matrix. These errors can be found in memory chip arrays, in magnetic tape recordings, or in the parallel-channel system with interference. In this study, the authors will build an algorithm for computing term-rank of a matrix and new construction of term-rank codes. Single error-correcting codes in the term-rank metric are considered and help us build a generator matrix and parity-check matrix for term-rank codes. Research results derived from this study show that the term-rank metric is suitable for correcting crisscross errors.

Codes for Limited Magnitude Error Correction in Multilevel Cell Memories

Multilevel cell (MLC) memories have been advocated for increasing density at low cost in next generation memories. However, the feature of several bits in a cell reduces the distance between levels; this reduced margin makes such memories more vulnerable to defective phenomena and parameter variations, leading to an error in stored data. These errors typically are of limited magnitude, because the induced change causes the stored value to exceed only a few of the level boundaries. To protect these memories from such errors and ensure that the stored data is not corrupted, Error Correction Codes (ECCs) are commonly used. However, most existing codes have been designed to protect memories in which each cell stores a bit and thus, they are not efficient to protect MLC memories. In this paper, an efficient scheme that can correct up to magnitude-3 errors is presented and evaluated. The scheme is based by combining ECCs that are commonly used to protect traditional memories. In particular, Interleaved Parity (IP) bits and Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes are utilized; both these codes are combined in the proposed IP-DAEC scheme to efficiently provide a strong coding function for correction, thus exceeding the capabilities of most existing coding schemes for limited magnitude errors. The SEC-DAEC code is used to detect the cell in error and correct some bits, while the IP bits identify the remaining erroneous bits in the memory cell. The use of these simple codes results in an efficient implementation of the decoder compared to existing techniques as shown by the evaluation results presented in this paper. The proposed scheme is also competitive in terms of number of parity check bits and memory redundancy. Therefore, the proposed IP-DAEC scheme is a very efficient alternative to protect and correct MLC memories from limited magnitude errors.

Energy-Adaptive Error Correcting for Dynamic and Heterogeneous Networks

In an era of ever-increasing dynamicity and heterogeneity of wireless networks, energy is fast becoming the most constrained resource. First, we review recent studies that suggest that using one single error-correcting code (ECC) designed to meet the worst case requirement is inefficient in terms of energy consumption when there are many heterogeneous nodes in the network. These works extend the classical Shannon theory and incorporate circuit energy and signal transmit energy to optimize total energy/power consumption of today’s communication systems. Then, we survey recent work on designing adaptive ECCs to operate energy efficiently even in the presence of extremely large heterogeneity in requirements and conditions. Two constructions of energy-adaptive codes are summarized: energy-adaptive low-density parity-check (LDPC) codes and energy-adaptive polar codes. These constructions have shown theoretically and empirically that having adaptivity in code design can save substantial energy, especially when the network has very diverse communication scenarios. Finally, we suggest a few possible applications where energy-adaptive codes can be employed and outline interesting future directions and challenges.

Efficient Implementations of 4-Bit Burst Error Correction for Memories

In recent years, there has been a growing interest in error correction codes (ECCs) that can correct localized errors in memories. This is due to the larger fraction of radiation induced error events that affect several nearby memory cells as technology scales. Initially, codes that can correct single and double adjacent errors were proposed. More recently, 3-bit burst ECCs have also been presented. The next step is to provide efficient 4-bit burst error correction for memories. The issue is that as the error correction capability increases so does the overheads required to implement the codes in terms of parity check bits and encoding and decoding complexity. In this brief, efficient solutions to protect memories against 4-bit bursts are presented. The first one is the use of two interleaved single and double adjacent ECC while in the second, efficient 4-bit burst ECCs are presented. The first solution reduces the decoding complexity and delay at the cost of having more parity check bits while the second tries to reduce the decoding complexity when using the minimum number of parity check bits. Both solutions have been evaluated and compared to an interleaved single error correction code and with existing burst ECCs to better understand the overheads needed to achieve the protection against 4-bit burst errors.

Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM

As one promising candidate of next generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-MRAM) offers many attractive characteristics, such as high speed, nonvolatility, high integration density, and excellent CMOS process compatibility. However, the performance and reliability of STT-RAM cells are greatly affected by device operating uncertainties and external circuit variation. As a result, write operations of STT-MRAM are not identical, which introduces asymmetric write failure rates for 0→1 and 1→0 bit flipping. Error correcting codes (ECCs) are general solutions for protecting memories from errors. The ECCs most widely used in memory technology are the single error correction and double error detection (SEC-DED) codes. Unfortunately, existing SEC-DED code schemes have limited correction capabilities and do not take the different error rates of memories into consideration. Regarding the failure characteristics (e.g., multibit and asymmetric) of STT-MRAM, conventional SEC-DED codes are not efficiently applicable. In this paper, we propose a proactive correction coset decoding scheme to correct double asymmetric errors for STT-MRAM. The scheme is partitioned into two levels: the proactive correction level (PCL) and the asymmetric correction level (ACL). The PCL proactively handles the single-bit error correction and the ACL analyzes the result from the prior level and corrects the second error. These levels are all based on the same standard coset array. Finally, simulation results with an SEC-DED code show the effectiveness and improvement of the proposed decoding scheme.

A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits

Many systems have critical bits which must be decoded at high speeds; for example, flags to mark the start and end of a packet (SOP and EOP) determine subsequent actions, thus they must be decoded first and fast. This paper presents a new single and adjacent error correction (SAEC) code; as the codewords have critical bits, the proposed code accomplishes a fast decoding for them. The proposed code is a systematic code and permits shortening. This is accomplished by reducing the information bits, so that columns in the H matrix can be eliminated, while still keeping both the SAEC capability and the systematic feature, but for an odd number of information bits, an adjustment step in critical bits is required. It is shown that the check bit length of the proposed code is nearly the same as that of the traditional (optimal) Hamming SAEC code. The decoder of the proposed SAEC code is compared with the traditional Hamming SAEC code; this comparison shows that on average, the delay time for the critical bits is reduced by 6 percent compared with the traditional Hamming SAEC code (so at the same reduction level as a previous SEC scheme for fast decoding of critical bits over a traditional SEC code). Also, the area and power consumption of the proposed decoder show average reductions of 12 percent and 10 percent compared with the decoder of a traditional SAEC code.

Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection

Soft errors produced by radiation events can cause malfunctions in modern day electronics. To preserve the system functionality, its elements must be protected against the effects of these events. Two of the possible techniques usually employed to implement fault tolerant registers are triple modular redundancy (TMR) and single error correcting (SEC) codes. However, the use of these techniques increases circuit area, timing, and power consumption to different extents. In this paper, we study the influence of each of these approaches on the circuit when they are implemented in application-specific integrated circuits and, based on the results, present some guidelines to choose between both of them depending on the design requirements. Additionally, we present a new low power fault tolerant technique destined for registers in which a subset of bits have a lower switching activity than the rest. This approach is based on the idea of combining TMR and SEC codes within a register to implement a hybrid protection that can exploit the strengths of each of the techniques. Our results show that the use of this technique achieves both power and area savings with respect to TMR in most cases, whereas it achieves large power savings with respect to SEC codes at the cost of increasing the area overhead.

Compact CA-Based Single Byte Error Correcting Codec

Memory contents are usually corrupted due to soft errors caused by external radiation and hence the reliability of memory systems is reduced. In order to enhance the reliability of memory systems, error correcting codes (ECC) are widely used to detect and correct errors. Single bit error correcting with double bits errors detecting codes are generally used in memory systems. But in case of multiple cell errors, these codes are unable to detect and correct errors. Recently, single byte error correcting Reed Solomon (SEC-RS) codes are used to detect and correct single byte error in memory systems. In this paper, a new single byte error correcting (SEC) code is proposed based on the concept of cellular automata (termed as CASEC). The main aim of this work is to reduce the area and power of SEC encoder and decoder circuit without affecting delay. In this paper, CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) and 2xCASEC(19,6,4) codecs are designed and implemented. CASEC(18,16,8) codec has 67.79 percent lesser hardware complexity compared to existing design. Proposed codecs are simulated and synthesized for both FPGA and ASIC platforms. It is found that speed of the proposed design is almost equal to the existing design but requires lesser area and power. Area-delay product (ADP) of proposed CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) codecs are better compared to the existing designs.

High speed Single Symbol Error Correction Codes Based on Reed Solomon Codes using verilog

High speed Single Symbol Error Correction Codes Based on Reed Solomon Codes using verilog

Study of proton radiation effect to row hammer fault in DDR4 SDRAMs

This paper shares the effects of row hammer fault through high-energy proton radiation. The significance of row hammer fault is highlighted in terms of two different technologies in DDR4 SDRAM.Row hammer stress prevents nearby storage cells from maintaining storage data within the retention time of 64-ms. The stress is worsened by the radiation damage in silicon due to the high-energy particles.Proton-based radiation damage tests were performed with DDR4 SDRAM components from two different technologies. Experiment results showed that after proton irradiation, the number of bit errors caused by the row hammering test increased about 41% and 66% in technologies 2x-nm and 2y-nm, respectively. With 2y-nm technology, bit errors started to appear from 5K Number of Hammering (NHMR)—the equivalent of 500-μs retention time. For 2y-nm components, more than 90% of failed words had multiple failed cells, which could not be corrected by Single Error Correction and Double Error Detection (SEC-DED) codes.

Combined Modular Key and Data Error Protection for Content-Addressable Memories

Content-addressable memories (CAMs) are a type of memory that receives an input search key and compares it to every entry of a table of stored keys. If there is a match, they return the corresponding address where the value was found. Alternatively, they can include a related Random Access Memory (RAM) that is accessed with the matching address, returning the corresponding data values. To protect a CAM with associated RAM against errors, parity or error-correction codes (ECCs) are typically used. They usually protect the CAM and the RAM information separately incurring in additional storage needs. This paper proposes a scheme to protect some configurations of CAM with its associated RAM from errors with a single ECC code. This ECC code can be used to provide advanced error correction to the combination of the key and data values stored in the CAM and the RAM, but it can also be applied in a modular way to provide simpler protection to the key or to the values individually.

Optimizing the Implementation of SEC–DAEC Codes in FPGAs

Single error correction and double-adjacent error correction (SEC–DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes methods to optimize the decoder of SEC–DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations.