Single-ended Power Amplifier Research Articles

Design of a Ka-band power amplifier

This paper introduces the design of a type of power amplifier working in the Ka-band, which has three stages based on 45nm CMOS technology. The operating frequency is 25-27GHz, and it has good efficiency and linearity. Among them, the driving stage adopts a cascode structure, the power stage adopts common source structure, and the matching network adopts a transformer structure. Using Cadence Virtuoso for simulation at the operating voltage of 1.8V, power gain of the single-ended power amplifier is 44.76 dB, saturation output power is 14.66 dBm, the output power at the 1dB compression point is 12.9dBm, and corresponding power-added efficiency is 22.19%.

Automatic Methodology for Wideband Power Amplifier Design

This letter presents an automatic power amplifier (PA) design methodology that uses a multidimensional search algorithm to find the best compromise between fundamental and harmonic impedance terminations for a specified bandwidth. In conventional design methodologies, PA designers need to preselect the optimum impedances, which normally follow non-Foster trajectories, and are thus impossible to achieve with passive matching networks (MNs) for a wide frequency range. Instead, the proposed automatic design method directly synthesizes the MNs to achieve the desired output power, efficiency, and gain performance, without forcing any impedance profiles. For that, load-pull data are interpolated using artificial neural networks and an algorithm based on the simplified real frequency technique is used to obtain the MNs. Finally, the method is validated with a single-ended PA implementation.

A SiGe Power Amplifier With Double Gain Peaks Based on the Control of Stationary Points of Impedance Transformation

A broadband SiGe power amplifier (PA) with double gain peaks for 5G applications is presented. The differential structure is widely adopted in millimeter-wave circuit design to decrease the impact of the source parasitic inductance that is induced by the bonding wires. Since differential PA results in a higher impedance transformation ratio of the matching network, differential PAs generally have narrower bandwidth than single-ended PAs. Through the bandwidth analysis of the matching network, the transformer used for interstage matching is elaborately designed to ease gain fluctuations. By controlling the stationary points of impedance transformation, the maximum available gain characteristic of a transistor, which decreases with increasing frequency, can be compensated. The gain curve of PA, thus, has double gain peaks within operational frequencies to make its frequency responses as flat as possible. The proposed PA for the frequency band from 27 to 37 GHz is fabricated in a standard 130-nm SiGe BiCMOS process, which occupies 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under the 2.5-V voltage supply, the SiGe PA exhibited a power gain of 33.5 dB and output power of 21.3 dBm with 24% power-added efficiency at 31 GHz. It achieves a 34% 3-dB small-signal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S_{21}$ </tex-math></inline-formula> bandwidth from 27.3 to 38.5 GHz.

D-Band SiGe BiCMOS Power Amplifier With 16.8dBm P₁dB and 17.1% PAE Enhanced by Current-Clamping in Multiple Common-Base Stages

This letter presents single-ended and differential $D$ -band power amplifiers (PAs) in 55nm SiGe BiCMOS technology. The proposed PAs exploit the remarkable features of common-base stages for rising the power efficiency, i.e., 1) higher breakdown voltage; 2) sharp compression profile due to the enhanced linearity; and 3) supply current adapted to the signal amplitude by means of current clamping. A four-stage single-ended PA proves ${P}\,\,_{\mathrm {1\,dB}}\,\,=16.8$ dBm with ${P}\,\,_{\text {SAT}}\,\,=17.6$ dBm at 135 GHz. The PAEs at ${P}~_{\mathrm {1\,dB}}$ and ${P}\,\,_{\mathrm {1\,dB-6\,dB}}$ are 17.1% and 8.5%, respectively. With a differential PA, the linear output power is increased to ${P}\,\,_{\mathrm {1\,dB}}\,\,=18.5$ dBm with ${P}\,\,_{\text {SAT}}\,\,=19.3$ dBm at 135 GHz. The PAEs at ${P}~_{\mathrm {1\,dB}}$ and ${P}\,\,_{\mathrm {1\,dB-6\,dB}}$ are 12.6% and 6.7%, respectively. The PAs demonstrate $3\times $ PAE improvement in the linear region against the state of the art.

Nonlinear distortion of angle modulation signal in output power amplifiers

The output power amplifier is operated in nonlinear mode to increase its efficiency, at which the signal is distorted more. The goal is to analyze effects of nonlinearity on the modulating signal of angle-modulated signal distortions for single-ended and push-pull output power amplifiers with memory and without it. The amplifier characteristic ic(vBE) is preset by the cubic polynomial. The output voltage of memoryless amplifier uout(t) is found by Ohm's law. And in case with amplifier with memory, the output voltage uout(t) is found by Complex amplitude method with a Fourier series of function ic(t). The output voltage uout(t) is represented as the narrowband process with envelope of the waveform U1(t) and initial phase Ф1(t) to determine the angular modulation law Ф1(t) at the amplifier output. The function U1(t) is defined as combination of in-phase А(t) and quadrature В(t) components. The distortion estimate based on Total Harmonic Distortion (THD). The measurement of THD is defined as the ratio of the RMS amplitude of a set of higher harmonic frequencies to the RMS amplitude of the first harmonic. The spectrum of function Ф1(t) is represented a Fourier series. In single-ended memoryless amplifier and non-cutoff mode, the THD decreases as m increases and THD of modulating signal is {37.6; 18.8; 6.3%} at m {0.5; 1; 3}. In cutoff mode, the smallest THD is {15.18; 5.13%} at m {1; 3} as θ = 140o. In push-pull memoryless amplifier and θ = 90o, the THD is {22.2; 11.1; 3.7%} at m {0.5; 1; 3} which is 1.7 times less than in a single-ended amplifier without cutoff. This is due to compensation even-order harmonic of amplified signal at the output of a pushpull amplifier. In this case of memoryless amplifier, the transistor load is a parallel RLC circuit. The distortion decreases under m increases at first (up m is 1.5), but then rapidly increases (from m is 1.7). This is due to increase of the parasitic harmonics level caused by the nonlinearity of the phase-frequency characteristic of RLC circuit. The calculations show that THD of modulating signal is 3.35, 9.02 and 22.88 % at Q = 10 and m {0.5; 1; 3}, respectively. In cutoff mode, the smallest THD is at θ = 90o and it does not depend on θ at large values of m. In push-pull amplifier with memory, the THD is 2.8, 2.5 and 3.0 times less than for a singleended amplifier without cutoff at Q {2.5; 5; 10}, respectively. The results of this paper can be used for the design of signal processing systems.

Design of low-power CMOS transceiver front end for 2.4-GHz WPAN applications

This paper describes the design of low-power direct conversion transceiver front end for WPAN (Wireless Personal Area Network) applications using TSMC 0.13 µm CMOS technology. Subharmonic mixers are proposed to mitigate the drawbacks of DC offset problem in direct conversion receiver and injection locking problem in direct conversion transmitter. The receiver front end comprises a low-noise amplifier (LNA), balun and subharmonic mixer. The direct conversion transmitter front end adopts a subharmonic passive mixer, differential to single-ended converter, driver and power amplifier. The post-layout simulation results produce voltage gain of 29 dB, noise figure of 5.84 dB, IIP3 of − 12 dBm and 1.79 mW consumption power for receiver front end at a supply voltage of 0.8 V. The transmitter front end achieves conversion gain of 15 dB, 0 dBm output 1-dB compression point (OP1dB) and 4.27 mW power consumption.

168-195 GHz Power Amplifier With Output Power Larger Than 18 dBm in BiCMOS Technology

This paper presents a 4-way combined G-band power amplifier (PA) fabricated with a 130-nm SiGe BiCMOS process. First, a single-ended PA based on the cascode topology (CT) is designed at 185 GHz, which consists of three stages to get an overall gain and an output power higher than 27 dB and 13 dBm, respectively. Then, a 4-way combiner/splitter was designed using low-loss transmission lines at 130-210 GHz. Finally, the combiner was loaded with four single-ended PAs to complete the design of a 4-way combined PA. The chip of the fabricated PA occupies an area of 1.35mm 2 . The realized PA shows a saturated output power of 18.1 dBm with a peak gain of 25.9 dB and power-added efficiency (PAE) of 3.5% at 185 GHz. A maximum output power of 18.7 dBm with PAE of 4.4% is achieved at 170 GHz. The 3-dB and 6-dB bandwidth of the PA are 27 and 42 GHz, respectively. In addition, the PA delivers a saturated output power higher than 18 dBm in the frequency range 140-186 GHz. To the best of our knowledge, the power reported in this paper is the highest for G-band SiGe BiCMOS PAs.

A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.

A Single-Ended Modified Class-E PA With HD2 Rejection for Low-Power RF Applications

This letter presents a fully integrated single-ended power amplifier for ultralow-power applications. The single-ended configuration is possible due to a choke-inductor less output network capable of rejecting the second-harmonic emission. A switching duty-ratio lower than 50% avoids the impedance transformation output network traditionally required for proper class-E operation. At 2.45 GHz, the PA (including the driver) delivers 1.4 dBm to a $50~ {\Omega }$ load and achieves an overall efficiency of 51% while complying with the spurious emission regulation. The prototype was fabricated in $0.13~ {\mu }\text{m}$ CMOS.

A Fully-integrated Highly Efficient CMOS Class-E Power Amplifier Using Cascode Class-E Drivers for WLAN Applications

This paper presents a modified class-E single-ended power amplifier (PA) for WLAN application. The proposed class-E PA consisting of two stages, all driver stages adopts bias voltage technique to simplify the structure and improves RF performance. The driver stage adopts the forward body bias technique to lower threshold voltage and realize high efficiency with low operation voltage; the power stage utilizes cascode topology with a self-biasing voltage technique to reduce device stress. The proposed PA is simulated by cadence IC in TSMC 0.18-μm CMOS technology. With a 2.3 V supply voltage, the fully integrated CMOS PA achieves maximum output power of 27.8 dBm and power-added efficiency (PAE) of 48.3% at 2.4GHz. It achieves high power gain of 31.5 dB and large output power with low input signal. The chip area of the proposed class-E PA is 0.90 mm2.

Hitting the Sweet Spot: A Single-Ended Power Amplifier Exploiting Class AB Sweet Spots and Optimized Third Harmonic Termination

The single-ended RF power amplifier (PA) is a standard design approach in the RF engineer?s tool kit, but high efficiency and good linearity may only be achieved if the harmonic terminations and biasing conditions are carefully examined. This is demonstrated in a single-ended PA using class-AB sweet spots and an optimized third harmonic termination, which won first place at the 2016 IEEE Microwave Theory and Techniques Society (MTT-S) International Microwave Symposium?s high-efficiency PA student design competition, sponsored by Technical Committee MTT-5.

A 70–80-GHz SiGe Amplifier With Peak Output Power of 27.3 dBm

This paper presents a fully integrated 16-way power-combining amplifier for 67–92-GHz applications in an advanced 90-nm silicon germanium HBT technology. The 16-way amplifier is implemented using three-stage common-emitter single-ended power amplifiers (PAs) as building blocks, and reactive $\lambda $ /4 impedance transformation networks are used for power combining. The three-stage single PA breakout has a small-signal gain of 22 dB at 74 GHz, and saturation output power ( $P_{\mathrm{ sat}}$ ) of 14.3–16.4 dBm at 68–99 GHz. The power-combining PA achieves a small-signal gain of 19.3 dB at 74 GHz, and $P_{\mathrm{ sat}}$ of 25.3–27.3 dBm at 68–88 GHz with a maximum power added efficiency of 12.4%. The 16-way amplifier occupies 6.48 mm2 (including pads) and consumes a maximum current of 2.1 A from a 1.8 V supply. To the best of our knowledge, this is the highest power silicon-based $E$ -band amplifier to date.

A 110–134-GHz SiGe Amplifier With Peak Output Power of 100–120 mW

This paper presents a fully integrated eight-way power-combining amplifier for 110-134-GHz applications in an advanced 90-nm silicon-germanium HBT technology. The eight-way amplifier is implemented using four-stage common-emitter single-ended power amplifiers (PAs) as building blocks, and reactive λ/4 impedance transformation networks are used for power combining. The single-ended PA breakout has a small-signal gain of 20 dB at 116 GHz, and saturation output power ( Psat) of 12.5-13.8 dBm at 114-130 GHz. The eight-way power-combining PA achieves a small-signal gain of 15 dB at 116 GHz, and Psat of 20-20.8 dBm at 114-126 GHz with a power-added efficiency of 7.6%-6.3%. The eight-way amplifier occupies 4.95 mm 2 (including pads) and consumes a maximum current of 980 mA from a 1.6-V supply. To our knowledge, this is the highest power silicon-based D-band amplifier to date.

A Single-chip Highly Efficient CMOS Class-E Power Amplifier for WLAN Applications

This paper presents a class-E, single-ended power amplifier (PA) for WLAN applications. This proposed circuit has a two-stage structure and adopts cascode class-E topology with self-biased technique that avoids using thick-oxide transistors and improves RF performance. The driver employing a current-reused technique can enhance the driving ability and power gain. Additionally, the efficiency is improved by inserting a series LC networks on drain node of switch transistor. The proposed PA is simulated by Advanced Design System (ADS) in TSMC 0.18-μ CMOS technology. With a 2.5-V power supply, the fully integrated CMOS PA achieves 21.5 dBm of maximum output power and 68.3% of power-added efficiency (PAE) at 2.4 GHz. It demonstrates a power gain of 45 dB and gives better output power at minimum input levels. The chip area including testing pads is 0.91 × 0.99 mm2.

Integrated CMOS RF transmitter with a single-ended power amplifier

This article presents a highly integrated CMOS RF double-sideband (DSB) transmitter (TX) including an active input balun and a single-ended power amplifier (PA) for a ultrahigh frequency radiofrequency identification (RFID) system-on-chip reader. The conventional TX architecture, including an up-conversion mixer and a balanced PA, requires an output balun to create the needed single-ended load. Compared to the conventional TX architecture, the proposed system provides a more compact circuit and uses a smaller chip area because the active balun and the single-ended PA have a much smaller size than those using a passive balun and a differential PA. In addition, the gain of the active balun, which is generally larger than unity, can be a benefit in the system design budget. The designed TX IC is fabricated using a 0.13 μm CMOS process on a small area of 780 × 560 μm2 (including pads). The TX IC exhibited an overall conversion gain of 41.7 dB, an output P1dB of 18 dBm, an OIP3 of 28 dBm, a DSB noise figure of 14.8 dB, and a power consumption of 284.4 mW, including the 42.9 mW consumed by the local oscillator buffer stages. The implemented TX IC complied with the spectral mask for the DSB amplitude-shift keying signal of the RFID reader at an output power of 15.5 dBm. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:205–210, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27257

An efficient CMOS power-combining technique with differential and single-ended power amplifier

This article proposes an efficient power-combining architecture with differential and single-ended power amplifiers (PAs) in a CMOS process. The single-ended amplifier is added for overall efficiency enhancement. To demonstrate this concept, a CMOS PA using the proposed architecture was fabricated with a 0.13-μm CMOS technology that delivers 30.6 dBm of output power with 42% drain efficiency and 38% power-added efficiency at 1.95 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2214–2217, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25460

A 2.4-GHz 0.18-μm CMOS Class E single-ended switching power amplifier with a self-biased cascode

This paper describes the design of a 2.4-GHz CMOS Class E single-ended power amplifier (PA) for WLAN applications in TSMC 0.18-μm CMOS technology. The Class E PA proposed in this paper employs cascode topology with a self-biasing technique to prevent device stress and to decrease the requirement for additional bond pads. Further, all inductors are realized by bondwires for high PA performance. The post-layout simulation results indicate that the PA delivers 23 dBm output power and 44.5% power added efficiency with 3.3 V power supply into a 50 Ω load.

Wide-band hybrid power amplifier design using GaN FETs

In this article, the design, fabrication, and testing of a wide band single-ended power amplifier (PA) using GaN field effect transistors (FETs) are reported. The single-ended amplifier demonstrates a bandwidth larger than 30% around 2 GHz, with a high gain, PAE, and output power combination. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.

A Quad-Band GSM/EDGE-Compliant SiGe-Bipolar Power Amplifier

A standard-compliant integrated quad-band GSM/EDGE radio frequency power amplifier for 824-915 MHz and 1710-1910 MHz has been realized in a 0.35-mum SiGe-Bipolar technology. The chip integrates two single-ended three-stage power amplifiers and control circuitry for band-select, power loop control and mode dependent quiescent currents. For power control, an on-chip voltage regulation loop is implemented, using an external P-channel MOS-transistor on a laminate module. At 3.3 V a saturated output power of 35.9 dBm is achieved at 830 MHz and 32.3 dBm at 1710 MHz. The respective peak power added efficiency (PAE) is 56% for low-band and 44% for high-band.

Highly Linear 0.18-&lt;tex&gt;$mu$&lt;/tex&gt;m CMOS Power Amplifier With Deep n-Well Structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.