Single-electron Transistor Logic Research Articles

SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET–CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 213 SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit.

Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation

Single-electron transistor (SET) circuits can be stacked above the CMOS platform to achieve functional and heterogeneous 3-D integration of nanoelectronic devices. For SET-CMOS hybridization, CMOS technology is essential for I/O, signal restoration, and maintaining compatibility with established technology. In spite of the SET's unparalleled advantages, its low current drive and output voltage when driving CMOS logic makes its use questionable in commercial ICs, specifically at the SET-CMOS interface. In this paper, we contribute to the design, analysis, and simulation of hybrid SET-CMOS circuits exploiting room-temperature operating SET technology. We developed an efficient computer-aided design tool to simulate large-scale SET and hybrid SET-CMOS circuits with conventional device elements. To demonstrate the SET logic driving capability for CMOS with interconnect parasitics, we analytically derived the SET logic parameters for the 22-nm technology node and used them to simulate hybrid SET-CMOS logic. We studied the performance of such hybrid logic circuit in terms of delay and bandwidth and addressed the tradeoffs between fabrication and electrical parameters. Our simulation results demonstrate the SET logic driving capability for CMOS comparable output voltage at gigahertz frequency in a hybrid SET-CMOS architecture. Finally, a comparison between SET and CMOS logic demonstrates that the SET logic outperforms CMOS.

Comparative study on the energy efficiency of logic gates based on single-electron transistor technology

The performance and the power consumption of single-electron transistor (SET) technology-based ultra-energy-efficient signal processing circuits are compared based on the SPICE model including non-ideal effects of the experimental data for the first time. In terms of ultra-energy-efficient logic circuits, the binary decision diagram (BDD) logic circuit is the most promising with a dissipated power of 0.29 nW at Vdd = 0.1 V and fin = 50 MHz among the static complementary metal-oxide-semiconductor (CMOS)-like SET logic, the dynamic SET/CMOS hybrid logic, cellular nonlinear network (CNN) and BDD. This result means that the transition of a paradigm substituting the current for the voltage as a state variable of a signal processing is strongly required in post-CMOS signal processing and ultra-energy-efficient applications.

Assessment of SET Logic Robustness Through Noise Margin Modeling

A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT). It is shown that choosing alpha=CT/CG=1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to plusmn0.03 e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that a isin [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.

Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation

This paper proposes, for the first time, the concept of programmable logic circuit realized with single-electron transistors (SETs). An SET having nonvolatile memory function is a key element for the programmable SET logic. The writing and erasing operations of the nonvolatile memory function make it possible to tune the phase of Coulomb oscillations. The half-period phase shift induced by the memory function makes the function of SETs complementary to that of the conventional SETs. As a result, SETs having nonvolatile memory function have the functionality of both the conventional (nMOS-like) SETs and the complementary (pMOS-like) SETs. By utilizing this fact, the function of SET circuits can be programmed with great flexibility, on the basis of the information stored by the memory functions. We have successfully fabricated SETs that operate at room temperature and observed the highest room-temperature peak-to-valley current ratio of Coulomb oscillations. The operation of the programmable SET logic is demonstrated using the room-temperature operating SETs. This is the first demonstration of room-temperature SET logic operation. The proposed programmable SET logic provides the potential for low-power, intelligent LSI chips suitable for mobile applications.

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.

Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.

Self-aligned double-gate single-electron transistor derived from 0.12-μm-scale electron-beam lithography

A single-electron transistor (SET) with two gates was fabricated via the self-aligned evaporation of Al into a trench structure comprised of Si and SiO2. The initial trench, which was comparable to 0.12 μm lines and defined by electron-beam lithography, was reduced to 0.05×0.02 μm by a slightly anisotropic etching characteristic. These processes allow for the production of SET devices using current silicon fabrication techniques. The simultaneous formation of two gates allows for one gate to be used to control the background charge of each device. The shift of Coulomb oscillation peaks was clearly shown by controlling the second gate bias. An inverter logic operation at a temperature of 5 K with a gain of 1.3 was obtained. These characteristics indicate that such SET logic devices, based on a combination of the good performance of the Al SET and the high level of control of the fabrication of Si technology, have considerable potential for future use.

A New Design Scheme for Logic Circuits with Single Electron Transistors

A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.