Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation

Abstract

Single-electron transistor (SET) circuits can be stacked above the CMOS platform to achieve functional and heterogeneous 3-D integration of nanoelectronic devices. For SET-CMOS hybridization, CMOS technology is essential for I/O, signal restoration, and maintaining compatibility with established technology. In spite of the SET's unparalleled advantages, its low current drive and output voltage when driving CMOS logic makes its use questionable in commercial ICs, specifically at the SET-CMOS interface. In this paper, we contribute to the design, analysis, and simulation of hybrid SET-CMOS circuits exploiting room-temperature operating SET technology. We developed an efficient computer-aided design tool to simulate large-scale SET and hybrid SET-CMOS circuits with conventional device elements. To demonstrate the SET logic driving capability for CMOS with interconnect parasitics, we analytically derived the SET logic parameters for the 22-nm technology node and used them to simulate hybrid SET-CMOS logic. We studied the performance of such hybrid logic circuit in terms of delay and bandwidth and addressed the tradeoffs between fabrication and electrical parameters. Our simulation results demonstrate the SET logic driving capability for CMOS comparable output voltage at gigahertz frequency in a hybrid SET-CMOS architecture. Finally, a comparison between SET and CMOS logic demonstrates that the SET logic outperforms CMOS.