Single Clock Signal Research Articles

Analysis, Calibration, and Performance Evaluation of a Generalized <inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula>-Phase Quadrature Phase Shift Frequency Selective Receiver

In this paper, a new low-power and blocker-tolerant receiver architecture, the generalized N-phase quadrature phase shift frequency selective (QPS-FS), is proposed and analyzed that is suitable for radio frequency (RF) energy harvesting networks. A complete comparative analysis of the N-phase QPS-FS receiver with conventional N-path passive mixer (P-M) receiver is also provided. The QPS-FS receiver utilizes the impedance translation concept to improve the receiver selectivity but eliminates the need of an active multiphase clock generation circuit used in the conventional N-path P-M receivers. It uses a single clock signal source at the desired signal carrier frequency and a phase shift network in the RF path of the receiver for frequency downconversion and quadrature (I/Q) demodulation. The QPS-FS receiver requires a slower clock signal source, the frequency of which is equal to the desired band RF signal carrier frequency ( $f_{c})$ as opposed to at least N/2 times $f_{c}$ for the conventional N-path P-M receivers. Consequently, the lower frequency clock source requirement extends the frequency coverage of the receiver by a factor of at least N/2 for a given clock source with a fixed maximum frequency. Reduction of the operating frequency and elimination of the active multiphase clock generation circuit would also eventually reduce the overall power consumption for the whole receiver system as confirmed through measurements. A wideband receiver calibration approach provides less than 2% of error vector magnitudes between the transmitted and received constellation points for various modulated signals having bandwidths up to 4 MHz.

P‐18: A Low‐Power Scan Driver Using Depletion‐Mode a‐IGZO TFTs for High‐Resolution Displays

AbstractIn this paper, a low‐power scan driver using depletion‐mode amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) is proposed for high‐resolution displays. The proposed scan driver uses single clock signal to reduce the power consumption. This scan driver is simulated at the operating frequency of 153.6 kHz, which is the driving condition of 10.0‐inch wide quadruple extended graphics array (WQXGA, 1600 × 2560) display with the frame frequency of 60 Hz. The power consumption of ten stages of the proposed circuit is 0.39 mW. The proposed scan driver reduces the power consumption by 69% compared to the conventional scan driver.

Design of High-Speed and Low-Power Two-Channel Pipeline ADC

This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.

Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems

In this paper, we formalize a novel multirate multidimensional folding (MMF) transformation, which is a tool used to systematically synthesize control circuits for pipelined very large scale integrated (VLSI) architectures that implement a restricted but immensely practical class, namely, rectangular decimators/expandors with line-by-line scan, of multirate multidimensional algorithms. Although multirate multidimensional algorithms contain decimators and expanders that change the effective sample rate of a discrete-time signal, it is possible using MMF to time multiplex the algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. MMF constraints are derived, and these constraints are used to address two related issues. The first issue is memory requirements in the folded architectures. We derive expressions for the minimum number of memory units required by a folded architecture that implements a multirate multidimensional algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints that indicate how a multirate multidimensional data flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of DSP applications that are based on multirate multidimensional algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms. Many design examples are considered to demonstrate the viability of MMF. It is shown that MMF is able to save 18-25% area for 1-4 level two-dimensional (2-D) discrete wavelet transforms (DWTs). A tradeoff between computational and storage area is highlighted by our study of a 2064/spl times/2064 4-level 2-D DWT. We also present a few 2-D IIR filter designs, where we are able to exploit the throughput bottleneck of these filters to derive extremely low area designs.

Synthesis of folded pipelined architectures for multirate DSP algorithms

In this paper we formalize a novel multirate folding transformation which is a tool used to systematically synthesize control circuits for pipelined VLSI architectures which implement multirate algorithms. Although multirate algorithms contain decimators and expanders which change the effective sample rate of a discrete-time signal, multirate folding time-multiplexes the multirate algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. Multirate folding equations are derived and these equations are used to address two related issues. The first issue is memory requirements in folded architectures. We derive expressions for the minimum number of registers required by a folded architecture which implements a multirate algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints which indicate how a multirate data-flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of digital signal processing applications which are based on multirate algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms.

Uniphase operation of a GaAs resistive gate charge-coupled device

The operation of a GaAs charge-coupled device (CCD) within the UHF band is a technically challenging problem. The GaAs CCDs that were reported previously in the literature were typically operated with multiphase clocks, with the majority operated using clocks in phase quadrature. To provide the multiple UHF clock wave forms with phase correlation to a GaAs CCD demands very stable picosecond timing accuracy between the adjacent clock phases, otherwise unpredictable variations will occur in the device performance. This requirement is difficult to achieve when attempting to incorporate a GaAs CCD in a high-speed analog application, such as the 500 MHz multichannel transient digitizer application being developed at TRIUMF, because of the nonlinear behaviour of the device as a load impedance. In addition to the difficult timing requirement, there are also the electronic circuit disadvantages associated with providing a multiphase clock to a GaAs CCD. The general circuit approach used to provide a multiphase UHF clock consists of splitting or dividing a master clock signal into a set of clock signals with the desired phase properties. The disadvantages of this approach are (i) the circuits are generally narrowband, restricting the range of clock frequencies that can be used; (ii) the circuits usually consume considerable power, producing substantial heat; and (iii) the circuits are typically complex, making them costly and difficult to incorporate with a GaAs CCD. A novel uniphase clock scheme was recently developed at TRIUMF that overcomes the above technical limitations for the UHF operation of a GaAs resistive gate CCD (RGCCD). The method is unique because the static transverse electric field within the GaAs RGCCD channel required to direct the motion of charge is established using the surface potential control offered by the resistive gates, under dc-biassed conditions. This permits a simple planar device comprising four electrodes per pixel to be used instead of a more elaborate castellated or ion-implanted device. Application of a single clock signal to the GaAs RGCCD provides the required temporal transverse electric field variation to cause charge motion to occur. Charge transfer efficiencies exceeding 0.999 have been achieved with a 128 pixel GaAs resistive gate CCD using (1) a fixed frequency uniphase clock operating below 100 MHz and (2) using a triggered dual frequency uniphase clock operating at 500 MHz during the signal acquisition period and at 15.6 MHz during the signal expenditure period.

One-phase CCD: a new approach to charge-coupled device clocking

A new approach to charge-coupled device (CCD) clocking has been developed that uses a single clock signal and dc bias on a device structure previously used for two-phase clocking. The one-phase approach results in improved operation by simplifying the clock circuit, reducing power consumption, and simplifying scanning of large CCD arrays.