Single-chip Module Research Articles

Evaluation of HPK [formula omitted] planar pixel sensors for the CMS Phase-2 upgrade

To cope with the challenging environment of the planned high luminosity upgrade of the Large Hadron Collider (HL-LHC), scheduled to start operation in 2029, CMS will replace its entire tracking system. The requirements for the tracker are largely determined by the long operation time of 10 years with an instantaneous peak luminosity of up to 7.5 × 1034cm−2s−1 in the ultimate performance scenario. Depending on the radial distance from the interaction point, the silicon sensors will receive a particle fluence corresponding to a non-ionising energy loss of up to Φeq= 3.5 × 1016cm−2. This paper focuses on planar pixel sensor design and qualification up to a fluence of Φeq = 1.4 × 1016cm−2.For the development of appropriate planar pixel sensors an R&D program was initiated, which includes n+-p sensors on 150mm (6”) wafers with an active thickness of 150µm with pixel sizes of 100×25 µm2 and 50×50 µm2 manufactured by Hamamatsu Photonics K.K. (HPK). Single chip modules with ROC4Sens and RD53A readout chips were made. Irradiation with protons and neutrons, as well was an extensive test beam campaign at DESY were carried out. This paper presents the investigation of various assemblies mainly with ROC4Sens readout chips. It demonstrates that multiple designs fulfil the requirements in terms of breakdown voltage, leakage current and efficiency. The single point resolution for 50×50 µm2 pixels is measured as 4.0µm for non-irradiated samples, and 6.3µm after irradiation to Φeq = 7.2 × 1015cm−2.

Testing and Assessment on the Short-Circuit Withstand Capability of Press-Pack IGBT Considering the Unbalanced Clamping Forces

Press-pack insulated gate bipolar transistors (PP-IGBTs) modules have become the mainstream choice in high-power-density applications such as breakers. Sufficient short-circuit (SC) withstand capacity is the key to the safe operation of power electronic equipment. However, the effect of the unbalanced clamping force, which is experienced frequently in the multichip PP-IGBT, on the SC withstand capacity needs to be studied. First, an SC withstand test platform is established to calibrate the critical energy for different voltage levels. Second, the SC process and the withstand capacity for different clamping forces are investigated experimentally. Combined with the finite-element simulation results, the effect of the clamping force on the SC withstand capability is analyzed, and the weak parts are pointed out. An evaluation method of SC withstand capacity considering the effects of the voltage levels and the clamping force is proposed. Finally, the effect of the unbalanced clamping force is experimentally studied using parallel single-chip modules (PPI), and the SC withstand test of a 3300-V/200-A multichip module with unbalanced clamping force is carried out. The results show that the clamping force has little effect on the critical energy, but the module with greater clamping force has worse SC withstand capacity.

Module development for the ATLAS Phase II Pixel Inner Tracker

The ATLAS experiment will undergo substantial upgrades to cope with the higher radiation environment and particle hit rates foreseen for HL-LHC. The phase II upgrade will include the replacement of the inner detector with a completely new silicon-based tracker. The ATLAS phase II Inner Tracker (ITk) will consist of hybrid pixel detectors and silicon strip detector layers. The innermost five-barrel layers and several endcap rings will be equipped with hybrid pixel detector modules. The modules are consisting of bare silicon modules connected to flexible printed circuits. Bare silicon modules are made of a silicon pixel sensor connected to either four FE chips to form a quad module or one FE chip to form a single chip module. The ITk phase II pixel community has conducted many developments geared towards meeting the necessary module production quality and throughput. These include establishing quality checking routines of bare module components, tooling developments for their assembly as well as electrical testing infrastructure to assess their operability to specification. A dedicated program to set in motion this effort and streamline these various stages was established using the RD53A front-end chip. Subsequent test and assembly work is being carried out using the ITkPix chips which are final size FE chips. This contribution will provide a detailed overview of these developments and their results in preparation for the ATLAS ITk pixel phase II upgrade module production.

Study of Electrical Contacts Fatigue and Degradation Evaluation for Press-Pack IEGT Under Power Cycling Tests

The electrical contact status between metal layers in a press-pack injection enhanced gate transistor (PP-IEGT) is essential information for the reliability of the whole device. This article employs the numerical method, microscopic detection, and power cycling test (PCT) to qualify the contact degradations and performance in PP-IEGT. First, the contact status of metal pair aluminum–molybdenum in a single-chip module is described through the finite element method (FEM). Then, the contact fatigue of the single-chip module is estimated by the microdetection of the chip surface and the monitor of contact resistance during PCT. Finally, PCTs are conducted on parallel branches to explore contact degradation under different contact statuses. The results show that the chip is subjected to fretting wear and cracks due to the periodic expansion and shrink. In the aging process, the contact resistances display a linear growth trend and have a significant impact on the electrical parameter shift. Moreover, the degradation of the branch with insufficient contact is more serious, especially under smaller clamping force and longer heating duration.

Analysis of Electronic Cooling with Natural Convection and Radiation

Abstract: The size of the electronic instruments as day by day decreases drastically and simultaneously the number of functions per chip increases hugely. So, it’s a great challenge to remove the heat generated by the chip efficiently. Many kinds of research works are going on in this direction for the past few decades. In this study the cooling effects of the chip are analyzed using CFD simulations. The single chip module is modelled using space claim. The analysis is carried out in static module by solving the governing equations for a flow through a channel via obstruction. The laminar flow is assumed for the temperature variation analysis in the chip. The three metals are copper, aluminium and silver are analyzed for temperature variation in chip. Form this analysis it wasfound that silver is the best metal to transfer the heat from the chip.

Design and implementation of smart home control system

This study designs a smart home control system, aiming to resloving family fires and the problem of children falling over windows. The system includes a data monitoring module, a single-chip control module, a display module, an executive module and an alarm module. The data monitoring module collects the temperature, smoke and pressure inside the home, and the single-chip microcomputer module processes the data collected by the data monitoring module and displays it on the display module in real time. When the temperature value exceeds the set threshold, the alarm module alarms; when the smoke concentration exceeds the lower limit of the set value, the executive module starts; when the smoke concentration exceeds the upper limit of the set value, the exhaust module starts, and the alarm module alarms and reminds that the smoke concentration is too high and need to prevent fire; When the monitored pressure at the window exceeds the set threshold, the drive module starts to close the window, in order to prevent children from falling. The design is simple in structure and low in cost, and can effectively prevent the occurrence of fire and children falling from windows.

Tuina Force Acquisition System of Finger Pressing Therapy

A Tuina force acquisition system of finger pressing therapy is discussed. Based on STC12C5A60S2, a display platform for Tuina force acquisition is designed. The hardware of the system is mainly composed of minimum system module, signal acquisition module, amplification and filtering circuit, sound and light alarm module and display module. The system is initialized at startup and adjusted to data acquisition state. When the doctor starts to massage, the measured data by sensor is transmitted to data acquisition system, then transmitted to host computer after processed by single-chip module. The data is displayed real-timely and dynamically on host computer and judged whether or not to generate alarm according to the preset threshold. When the sensor prober is placed on his upper arm, and mechanical stimulation is performed using finger-pressing therapy, the system can collect and display finger-pressing massage force accurately in real time. Experiments show that the system can collect massage force quickly and effectively in real time.

Radiation resistant innovative 3D pixel sensors for the CMS upgrade at the High Luminosity LHC

Results of an extensive R&D program aiming at radiation hard, small pitch, 3D pixel sensors are reported. The CMS experiment is supporting this R&D in the scope of the Inner Tracker upgrade for the High Luminosity phase of the CERN Large Hadron Collider (HL-LHC). In the HL-LHC the Inner Tracker will have to withstand an integrated fluence up to 2.3×1016neq/cm2. A small number of 3D sensors were interconnected with the RD53A readout chip, which is the first prototype of 65 nm CMOS pixel readout chip designed for the HL-LHC pixel trackers. In this paper results obtained in beam tests before and after irradiation are reported. The irradiation of a single chip module was performed up to a maximum equivalent fluence of about 1×1016neq/cm2. The analysis of the collected data shows excellent performance: the spatial resolution in not irradiated sensors can reach about 3 to 5 μm, for inclined tracks, depending on the pixel pitch. The measured hit detection efficiencies are close to 99% measured both before and after the above mentioned irradiation fluence.

Minimizing Temperature Nonuniformity by Optimal Arrangement of Hotspots in Vertically Stacked Three-Dimensional Integrated Circuits

Abstract The semiconductor packaging technologies have seen its growth from multichip module (MCM), system in package (SiP), system on chip (SoC) to the heterogeneous integration of the MCM. Thermal management of multichip vertically integrated systems poses additional constraints and limitations beyond those for single chip modules. Three-dimensional-integrated circuits (3D ICs) technology is a potential approach for next-generation semiconductor packaging technologies. A 3D IC is formed by vertical interconnection of multiple substrates containing active devices which offer reduced die footprint and interconnect length. This paper discusses the optimal arrangement of two hotspots on each layer of a two-die stacked 3D IC. An analytical heat transfer model for prediction of three-dimensional temperature field of a 3D IC based on the solution of governing energy equations has been developed and used for this study. The model is subject to adiabatic boundary conditions at the walls except for the bottom wall which is subject to convective boundary condition. A feed-forward back propagation artificial neural network (ANN) is employed for obtaining the functional relationship between the location of the hotspots and the objectives. Genetic algorithm is employed for solving two nonconflicting objective functions subject to set of constraints. The first objective aims to minimize the maximum temperature on both layers, and the second objective aims to achieve temperature uniformity in the layers. The results of the optimization study are expected to provide recommendations on the design guidelines for arranging hotspots on vertically stacked substrates.

Влияние топологии многокристальных IGBT-модулей на распределение тока между транзисторными чипами в статических режимах работы

Factors affecting the distribution of direct current among parallel transistor chips in a multichip IGBT module are experimentally investigated. The voltage-current characteristics (VCCs) of single-chip modules with the rated operating current equal to 200 A and voltage equal to 1200 V in the collector current range from 50 to 200 A at temperatures equal to 25, 90, 120 and 150°C were measured to evaluate the compensation ability of the saturation voltage positive temperature dependence. A comparative experiment on measuring the voltage drop across individual parts of the conductors system composed of samples of IGBT modules with different topologies based on the half-bridge circuit arrangement and having three parallel-connected chips in passing a 400 A direct current through the module was carried out. It has been found from the experimental results that the use of the saturation voltage positive temperature dependence for equalizing the current distribution between the chips has limited capabilities, and that one of possible methods for achieving this is to use the resistance of a system of aluminum conductors. Comparative tests were carried out for estimating the stability of modules with different topologies to the effect of cyclic current load in a mode facilitating accelerated degradation of the soldered seam between the chip and the DBC substrate. The experimental results confirm the importance of considering the factors affecting the static current distribution between the chips in designing the topology of multichip IGBT modules.

Resource Sharing in Dual-Stack Devices: Opportunistic Bluetooth Transmissions in WLAN Busy Periods

The coexistence problem of different wireless protocols that share a common frequency spectrum has attracted much attention owing to the proliferation of heterogeneous wireless networks in the research community. Recently, Bluetooth (BT) and Wireless LAN (WLAN) protocol stacks have been integrated as a single-chip communication module, and they now even share the antenna as well as the spectrum. In this paper, we show that this integration provides new opportunity for one protocol to better understand the other and to operate in harmony to avoid mutual interference. We develop an Opportunistic Bluetooth Transmission (OBT) scheme that enables a dual stack device having an integrated module to exploit previously-unused deferring times of the WLAN protocol. We evaluate its performance through not only model-based analysis but also practical implementation in a prototype testbed. The results show that the OBT scheme can significantly improve throughput of the dual-stack device.

Design of An Intelligent Split-type Electricity Utilization Measurement and Control Terminal for Local Household Energy Management and Optimization

It is of great significance to implement automatic demand response (ADR) in the energy Internet based on accurate measurement and control of electricity utilization devices using intelligent terminals. Current intelligent terminals lack flexibility and possess weak data collection and processing capabilities. On this basis, this paper developed an intelligent split-type electricity utilization measurement and control terminal for local household energy management and optimization. This intelligent terminal has capabilities of digital signal processing and infrared-based precision control, which is composed of two separate parts: the device body and the infrared controller. Among them, the device body includes DSP chip, electrical sampling circuit, ADC chip, WiFi module, ZigBee module, etc. The infrared controller contains single-chip microcomputer, ZigBee module, infrared encoding and transmit-receiving module, and lithium-ion battery. The device body is able to provide commands to the infrared controller according to the collected electricity utilization information, environmental information and comprehensive demand response requirements, thereby accurately adjusting the operating status of the loads, namely the electrical household appliances. Due to the split-type and rechargeable design, this intelligent terminal is able to adapt to a complex home environment, laying the hardware foundation for effective home energy management and optimization and facilitating household loads participating in demand response, especially automatic demand response.

Packaging of High-Gain Multichip Module in Multilayer LCP Substrates at $W$ -Band

In this paper, we packaged a multichip module (MCM) in multilayer liquid crystal polymer (LCP) substrate using V-shaped wire bond and 3-D-printed housing. In the proposed module, two low-noise amplifiers (LNAs) are cascaded in series to obtain high gain and low noise figure, and multilayer circuit is designed to achieve high assembly density. To minimize mode mismatch between microstrip lines on LNA and LCP with low dielectric constant, V-shaped wire bond was designed for LNA integration, achieving low insertion loss and low reflection at $W$ -band. To verify this bonding design experimentally, a single-chip module was first integrated and characterized, successfully achieving a gain of more than 26.5 dB from 80 to 100 GHz. Then, the MCM was investigated and packaged, in which substrate integrated waveguides and via barriers are introduced to eliminate the potential substrate modes, and 3-D-printed plastic housing coated with gold is designed to capsulate the LNAs and isolate them in free space. The measured data demonstrate a high gain of 50 dB, a low noise figure of less than 6 dB, and linear phase from 80 to 97 GHz.

Mechanical packaging, power, and cooling design for the IBM z13

The system-level packaging of the IBM z13™ supports the implementation of a new drawer-based Central Processor Complex (CPC). Departing from previous IBM z Systems™ designs, the introduction of distributed land-grid-array (LGA) attached single-chip modules (SCMs) required new mechanical, power, and cooling designs to address specified performance requirements and to provide enhanced reliability, availability, and serviceability (RAS) attributes. Building upon the designs created for the IBM zEnterprise® BC12 (zBC12), new CPC drawer and frame mechanical designs were created to significantly increase overall packaging density. Similar to its predecessor, the IBM zEnterprise EC12 (zEC12), the z13 utilizes water-cooling of the processors, but in contrast to the single input and return flow used to cool the multi-chip module (MCM) in the zEC12, the z13 accomplishes its processor cooling using a flexible hose internal manifold design that provides parallel input and return fluid flow to each SCM. The use of flexible hose also enabled SCM field replacement, new to high-end IBM z Systems. A new internal cooling loop unit and an updated external (building-chilled) modular water-conditioning unit were designed utilizing customized water delivery manifold systems to feed the common CPC drawer design. Revised power delivery and service control structures were also created to address the distributed nature of the z13 system design.

The IBM z13 processor cache subsystem

The IBM z13™ system introduces many new innovative concepts in building a high-performance modular and scalable symmetrical multiprocessing (SMP) system, comprising up to 192 multithreaded processors that span eight system processing nodes. The z13 uses new socket packaging technology, changing from multichip modules (MCMs) to single-chip modules (SCMs). This enables the modularity and scalability of a large distributed SMP system and led to the development of new techniques in several important performance areas. For the cache hierarchy, the inclusivity management policy is optimized between the third-level and the fourth-level shared caches to improve overall cache-bit efficiency, effectively making the fourth-level cache larger to reduce the impact of increased chip socket-to-socket access latencies. The system bus management is enhanced such that multiple data transfers can be simultaneously overlapped on an interface to reduce wait times on critical data when these buses are highly utilized. With the amount of caches on both the Central Processor (CP) and System Controller (SC) chips, several major improvements were made for array macro resiliency to improve overall system availability. These and other major design updates in the latest mainframe processor cache subsystem are described in this paper.

Beam test characterization of CMS silicon pixel detectors for the phase-1 upgrade

The Silicon Pixel Detector forms the innermost part of the CMS tracking system and is critical to track and vertex reconstruction. Being in close proximity to the beam interaction point, it is exposed to the highest radiation levels in the silicon tracker. In order to preserve the tracking performance with the LHC luminosity increase which is foreseen for the next years, the CMS collaboration has decided to build a new pixel detector with four barrel layers mounted around a reduced diameter beam pipe, as compared to the present three layer pixel detector in the central region. A new digital version of the front-end readout chip has been designed and tested; it has increased data buffering and readout link speed to maintain high efficiency at increasing occupancy. In addition, it offers lower charge thresholds that will improve the tracking efficiency and position resolution. Single chip modules have been evaluated in the DESY electron test beam in terms of charge collection, noise, tracking efficiency and position resolution before and after irradiation with 24GeV protons from the CERN Proton Synchroton equivalent to the fluence expected after 500fb−1 of integrated luminosity in the fourth layer of the pixel tracker. High efficiency and an excellent position resolution have been observed which are well maintained even after the proton irradiation. The results are well described by the CMS pixel detector simulation.

SiGe BiCMOS high‐gain and wideband differential intermediate frequency amplifier for W‐band passive imaging single‐chip receivers

This thesis presents solutions and studies related to the design of reconfigurable and wideband receiver circuits for system-on-chip (SoC) radiometer front-ends within the millimetre-wave (mm-wave) range. Whereas many of today’s mm-wave front-ends are bulky and costly due to having discrete RF components, single-chip receiver modules could potentially result in a wider use for emerging applications such as wireless communication, short range radar and passive imaging security sensors if realised with adequate performances and at a lower cost. Three main topics are considered in this thesis, monolithic integration of low-loss RF-MEMS (Dicke) switch networks and switched LNAs in MMIC/RFIC foundry processes, designs of SiGe wideband (IF) amplifier and broadband power detectors up to W-band (75-110 GHz).Low-loss and high isolation GaAs and SiGe RF-MEMS switch networks were designed and characterised for the 30-110 GHz range. A GaAs MEMS Dicke switch network has a measured minimum loss of 1 dB and maximum isolation of 19 dB at 70-96 GHz, respectively, making it a potential candidate in Dicke switched radiometer receivers. Furthermore, single-chip 30 GHz and W-band MEMS Dicke switched LNA designs have been realised for the first time in SiGe BiCMOS and GaAs mHEMT processes, respectively.For a targeted 94 GHz passive imaging application two different receiver topologies have been investigated based on direct-detection and direct-conversion (heterodyne) architectures. An optimised detector design fabricated in a 0.13 μm SiGe process achieves a more wideband input matching than earlier silicon W-band detectors and is competitive with reported III-V W-band detectors in terms of a higher responsivity and similar NEP.A SiGe 2-37 GHz high-gain differential (IF) amplifier design achieves a more wideband matching and an order of magnitude higher linearity than a recent single-ended SiGe LNA. The SiGe IF amplifier was integrated on-chip with a power detector in a 5-35 GHz IF section. Their broadband properties compared with other IF amplifier/detector RFICs, make them suitable for W-band down-conversion receivers with a larger pre-detection bandwidth and improved sensitivity. The experimental results successfully demonstrate the feasibility of the SiGe 5-35 GHz IF section for high performance SoC W-band radiometers using a more wideband heterodyne receiver architecture.

Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package

In organic packages, large die and large laminate body sizes are susceptible to CTE (coefficient of thermal expansion) mismatch driven warpage, stresses and strains, which can result in C4 white bumps, micro Ball Grid Array (BGA) interconnection issues, and package thermal reliability concerns. Low CTE carriers minimize these concerns and allow increased chip join yields and improved package reliability. Modeling and characterization of warpage, chip and micro BGA integrity and electrical characterization of a low CTE, Chip Scale Package (CSP) were described in an earlier paper. In this paper we report the progress on the next phase - thermal and chip package interaction (CPI) evaluation of a single chip CSP designed for use with Multi-Chip Modules (MCM). Assembly, characterization, thermal performance and reliability stress results of these low CTE CSP Single Chip Modules (SCMs) are described. Measured warpage values are compared with thermo-mechanical modeling results. Demonstration of a dual CSP design and assembly with large dies is also presented. The successful demonstration of the material set, bond and assembly processes, and reliability of a large die, high I/O CSP, followed by the demonstration of a dual CSP on a multi component carrier, are fore-runners to the development of multi-CSP MCMs.

Designing of the Urban Public Bus Operation Dispatch System

The urban public bus operation dispatch system is one of the most important systems in ITS (Intelligent Transportation System). This paper describes the system in detail, including the system’s architecture, the bus onboard equipment and the system’s software part etc. Through integrating the single chip module, GPRS module, GPS module and other modules, the bus onboard equipment is designed. According to the object-oriented software engineering ideas and using UML (Unified Model language), the software system is designed. Finally, the bus onboard equipment and the system software part can send information each other using GPRS technology. The system has been implemented using Visual Studio 2005 C# language and tested in laboratory.

Carbon Nanotube Based Polymer Adhesive as an Underfill for Superconductor Multi-Chip Module Packaging

We report the development of a nano-engineered cryogenic adhesive (nECA) consisting of an epoxy impregnated with single walled carbon nanotubes (SWNT) for bonding niobium-based superconductor multi-chip modules (MCMs). The nECA offers 300%-900% enhancement in thermal conduction over the base adhesive while maintaining high electrical resistivity. Additionally, we report the thermal modeling results for a niobium-based superconducting single chip module with the incorporation of pure epoxy and nECA. When the heat flow is exclusively through the In/Sn bumps the thermal model predicts >; 100 mK temperature difference between the flipped chip with active circuitry and the passive carrier substrate, which might degrade the chip's performance and the operating margins. With the use of 0.1 wt% SWNT loaded epoxy as the underfill, we report reduction of temperature differences to a more acceptable level of ~ 19 mK. These results are expanded to foreseeable MCM package designs to highlight the merit of nECA as an underfill material for superconducting electronic packages.