Single-channel Successive Approximation Register Research Articles

A 1.38-mW 7-bit 1.7-GS/s Single-Channel Loop-Unrolled SAR ADC in 22-nm FD-SOI With 8.85 fJ/Conv.-Step for GHz Mobile Communication and Radar Systems

A 7-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with a sampling rate of 1.7 GS/s at a power consumption of 1.38 mW is presented. To prove the concept, the circuit was fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. It achieves an effective number of bits (ENOB) of 6.52 and a Walden figure-of-merit () of 8.85 fJ/conv.-step. High sampling speed is achieved by introducing optimized logic, heavily employing dynamic logic for the critical building blocks as the memory cells and clock logic. Sharing of reset transistors between multiple memory cells further reduces the delay between comparator decision and switching of the capacitive digital-to-analog converter (CDAC) by 15%. For calibration of the comparator offset, tuning of the back-gate voltage available in the FD-SOI technology is investigated and employed. Compared with conventional approaches using a separate differential input pair, this reduces the comparator power dissipation by 5% and its noise by 10%. The ADC operates on a single 800-mV supply and uses an active area of 0.0022 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The ADC is the fastest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 6-bit ENOB single-channel SAR (or pipelined SAR) ADC, while at the same time achieving the best for any previously reported ADC above 1 GS/s.

A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported.

A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step

We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross-Coupled Pair (HXCP) is proposed in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}_{\text {m}}$ </tex-math></inline-formula> -R based residue amplifier design as a critical part of the presented ADC. This technique overcomes the challenges in designing analog amplifiers using advanced nanometer CMOS processes and achieves the gain and linearity required for the ADC. By implementing the HXCP in a residue amplifier (RA), the proposed technique successfully improves the RA linearity by at least 10 dB and meanwhile boosts the gain of the RA to be about 8. The entire ADC consists of three stages each with 4-bit, 4-bit, and 6-bit, respectively. Two one-bit interstage redundancies are implemented between the three stages. Various techniques are also implemented to help the ADC achieve the targeted speed and resolution. The presented ADC was implemented in a 28nm CMOS process and achieves an ERBW of 1 GHz, an SNDR of 60.7 dB, an SFDR of 73 dB at Nyquist input (495 MHz) and an SFDR of 82 dB at 1 GHz input. A 7.5 fj/conv-step FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</sub> and a 169.4 dB FoMs are achieved, which demonstrate one of the best Figure of Merits (FoMs) among ADCs of similar speed and resolution.

A 12-b 1-GS/s 61-dB SNDR Pipelined-SAR ADC With Inverter-Based Residual Amplifier and Tunable Harmonic-Injecting Cross-Coupled-Pair for Distortion Cancelation Achieving 6.3 fJ/conv-step

A 1GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog-to-digital converter (ADC) is presented. It consists of three stages (4b-4b-6b) with two one-bit interstage redundancies implemented. A novel Harmonic-injecting Cross-Coupled Pair (HXCP) is proposed in an inverter-based residual amplifier (RA) as a critical part of the presented ADC. By implementing the HXCP, the linearity of the RA is effectively improved and meanwhile the gain of the RA is boosted to about 8. The HXCP is designed to be tunable to enhance its robustness against PVT variation. The prototype single-channel ADC was fabricated in 28-nm CMOS process and achieves &#x003E;60dB SNDR and &#x003E;70dB SFDR up to 320MHz, corresponding to a 6.3fJ/conv. step FoMw and 170.5dB FoMs.

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a $0.6~\mu m$ standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm $\times6.6$ mm. As for single channel SAR ADC, the area is 0.9mm $\times2.0$ mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier

A temperature-stabilized 12-bit single-channel successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to noise and distortion ratio (SNDR) above 60 dB is presented. The ADC uses a three-stage (4 b-4 b-6 b) SAR-assisted pipeline hybrid architecture to achieve an attractive energy efficiency along with an extended sampling rate. A high-linearity open-loop Gm-R-based residue amplifier (RA) with both complete-settled and dynamic features improves the residue amplification efficiency and speed, while reducing the gain variation over a temperature drift. The inter-stage gain variation over the temperature is compensated through complementary temperature coefficients (TCs) from the inner devices of the RA. Furthermore, a cascade amplification topology in the backend RA alleviates the effect of the input parasitic capacitance to its front-end capacitor DAC (CDAC), thus leading to a small CDAC size to accelerate amplification and conversion. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 7.6 mW from a 1-V power supply at 1 GS/s. The measured inter-stage gain variation is less than 2.3% with a temperature range from 0 °C to 80 °C. The SNDR and SFDR are 60 and 74.6 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 9.3 fJ/conversion-step and a Schreier FoM of 168.2 dB.

A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS

This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using background-calibrated coarse and fine comparators. A coarse and fine comparator scheme is proposed for the bit cycling procedure of MSBs and LSBs to reduce the power consumption. By employing a capacitive digital-to-analog converter (DAC) with redundancy, the decision errors of the coarse comparators due to the thermal noise can be tolerated. Therefore, coarse comparators can have relaxed noise constraint and consume low power. In addition, a novel background calibration method is proposed to align the offsets between different comparators using a reference comparator. This background calibration technique requires no additional bit cycle for comparator calibration, thus improving the ADC's conversion speed. The prototype ADC is implemented in a 28-nm CMOS technology and achieves an effective number of bits of 6.95 b (signal to noise and distortion ratio (SNDR) of 43.6 dB) near Nyquist frequency with the figure of merit (FOM) of 25.87 fJ/conversion-step. To the best of authors' knowledge, this ADC achieves the highest SNDR among all single-channel SAR ADCs reported that operate above 1 GS/s.

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

This paper presents a 1.25-GS/s 7-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analog-to-digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage $V_\mathrm{cm}$ . To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective $V_\mathrm{cm}$ - adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noise-plus-distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.

An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65 nm CMOS

This paper presents an 8-bit 500-MS/s asynchronous single-channel successive approximation register analog-to-digital converter (SAR ADC). A split capacitor array technique is applied to decrease t...

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional reference voltages are provided to reduce the number of unit capacitors in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offset is implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm2.