A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS

Abstract

This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using background-calibrated coarse and fine comparators. A coarse and fine comparator scheme is proposed for the bit cycling procedure of MSBs and LSBs to reduce the power consumption. By employing a capacitive digital-to-analog converter (DAC) with redundancy, the decision errors of the coarse comparators due to the thermal noise can be tolerated. Therefore, coarse comparators can have relaxed noise constraint and consume low power. In addition, a novel background calibration method is proposed to align the offsets between different comparators using a reference comparator. This background calibration technique requires no additional bit cycle for comparator calibration, thus improving the ADC's conversion speed. The prototype ADC is implemented in a 28-nm CMOS technology and achieves an effective number of bits of 6.95 b (signal to noise and distortion ratio (SNDR) of 43.6 dB) near Nyquist frequency with the figure of merit (FOM) of 25.87 fJ/conversion-step. To the best of authors' knowledge, this ADC achieves the highest SNDR among all single-channel SAR ADCs reported that operate above 1 GS/s.