Single Balanced Mixer Research Articles

IP2 optimization in frequency mixers using ferroelectric field-effect transistors

Ferroelectric devices have traditionally been utilized in memory circuits due to their ability to retain a polarization charge and potentially act as a nonvolatile storage device. Their usage in applications unrelated to memory has also previously expanded into other digital and analog circuits, and now, it is being investigated in radio frequency circuits. This work explores the implementation of a frequency mixer using ferroelectric field-effect transistors in order to demonstrate stability against voltage offsets in a single-balanced mixer, making use of the polarization in the switching transistors to improve the performance of the second-order intermodulation product.

A 195–244 GHz CMOS self-mixing frequency tripler with >23 dBc fundamental rejection

This paper presents a wideband and high-fundamental rejection self-mixing frequency tripler in a 40-nm CMOS. The proposed tripler consists of an input half-shielded transformer balun, an even-harmonics generator, a single-balanced mixer, a slow-wave coupling-line filter and an output half-shielded Marchand balun. The half-shielded coupling structure improves the coupling coefficient of the coupling-line components and also features high design freedom. Consequently, the half-shielded transformer balun achieves a broadband performance. The half-shielded Marchand balun achieves a 1-dB bandwidth of 109 GHz (49.7 %) and a minimum insertion loss of 1 dB. The slow-wave coupling-line filter enhances the fundamental rejection of the proposed tripler with low insertion loss of 1.5 dB, wide 1-dB bandwidth of 162 GHz (62.8 %) and compact footprint (0.01 mm2, 0.00535 λ2). The slow-wave coupling-line filter achieves a broadband low-frequency rejection over 18.6 dB from 65 to 88 GHz. Due to the above-mentioned technology, the tripler achieves a 3-dB bandwidth of 49 GHz from 195 to 244 GHz and a fundamental rejection larger than 23 dBc. Compared with the state-of-the-arts, the proposed self-mixing tripler features wide bandwidth, high fundamental rejection and compact core area among silicon-based triplers.

Design of a full V‐band fundamental mixer with an ultra‐wide IF from 0.01 to 22 GHz

Design of a low cost Schottky diode based single-balanced mixer (SBM) in full V-band with an ultra-wide intermediate frequency (IF) bandwidth is presented here. By loading multiple quarter-wavelength short-ended stubs at both radio frequency (RF) and local oscillator (LO) frequency on the multistage stepped impedance matching networks, a broadband grounding circuit is provided for IF signal and thus output power nulls are eliminated over an ultra-wide IF band. The hybrid network is constructed by a 3 dB branch coupler and a 90-degree delay line, which enables the required balanced outputs with equal amplitude and 180-degree phase difference. A prototype of the SBM is designed, fabricated and tested. Measured results demonstrate that, for RF and LO frequency over entire V-band, the mixer has a conversion loss from 6.8 to 11.4 dB with an ultra-wide IF range of 0.01–22 GHz.

A K/Ka/V Triband Single-Signal-Path Receiver With Variable-Gain Low-Noise Amplifier and Constant-Gain Phase Shifter in 28-nm CMOS

This article presents a single-signal-path tri (K/Ka/V)-band receiver (RX) featuring area/cost-effective support for various millimeter-wave phased-array applications. A triple-coupling transformer (TCT) at the common-gate input stage of the RX low-noise amplifier (LNA) is proposed for triband impedance matching and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting. By augmenting each low-parasitic pMOS switched inductor load with a pMOS variable resistor in parallel, the variable-gain functionality is merged into this LNA to cover a wide input-signal range in a low-overhead manner. An active single-balanced mixer (SBM) for radio frequency (RF)-intermediate frequency (IF) downconversion is adopted to eliminate a wideband balun. Poor RF-IF and local-oscillator (LO)-IF isolations and low IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> normally inherited in an SBM are avoided by setting the IF particularly. The wideband response of an on-chip LO buffer is realized through input resistor coupling and output inductor peaking. Furthermore, a constant-gain phase shifter (CGPS) at IF is proposed to benefit the orthogonal gain-and-phase control preferred by beam steering. This CGPS uses an amplitude-only feedback loop to retain the gain without baseband equalization. Fabricated in a 28-nm bulk CMOS technology, this RX exhibits variable power gains of 12.5-33.2 dB (at 24 GHz), 13.4-34.6 dB (at 33 GHz), and 3.1-32 dB (at 50 GHz) with respective minimum noise figures of 4.78, 5.12, and 6.15 dB. The respective RX 3-dB bandwidths are 20-27, 30-34.6, and 42-55.5 GHz. The measured CGPS gain variation at IF (2-4 GHz) is within 0.94 dB. This RX consumes 131 mW and occupies 1.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with pads in a silicon area.

A Differential Voltage-controlled Oscillator as a Single-balanced Mixer

This paper proposes a low power radio frequency receiver front-end where, in a single stage, singlebalanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of ‒72 dBc/Hz, ‒93 dBc/Hz, and ‒113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is ‒14.2 dB, ‒8.8 dB, and ‒7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 μW dc power from a 1-V supply.

Design & development of 140 GHz D-band phase locked heterodyne interferometer system for real-time density measurement

A 140 GHz phase-locked heterodyne interferometer system has been designed, developed and installed at Aditya Tokamak for real time density measurement. The interferometer uses a novel approach of zero-cross detection using in-phase and quadrature (IQ) signals with a single balanced mixer. The transmitter and receiver systems are phase locked by a 100 MHz crystal oscillator and the output signals are mixed in a single balanced mixer which produces highly stabilized intermediate frequency (IF) frequency of 2.0 GHz. This signal is further amplified by low noise amplifier (LNA) and power amplifier with built-in automatic gain control (AGC) of response time 5 ms. The AGC keeps the IF signal amplitude stable for 20–70 dB attenuation. This IF signal is further down converted to 100 KHz IQ signals using a synthesizer which is phase locked by the same 100 MHz crystal oscillator used for phase locking the transmitter and receiver oscillators. The 100 KHz IQ signals are digitized by built-in 12 bits ADCs and processed though FPGA programming for real time phase-density calculations. The developed system has minimum phase sensitivity of 0.07 radian and a time resolution of 5 μs with 10 KHz resolution for real time density measurement. The density evolution of plasma discharge and effect of gas puff on density built up is successfully measured in real time and presented in this paper.

A low conversion loss single balanced subharmonic mixer

A new circuit topology for the design of a single balanced second-order subharmonic mixer (SHM) is proposed. In the proposed topology, it is not necessary for the radio frequency (RF) and local oscillator (LO) signal to be within 15% frequency difference. Thus, the limitation of a conventional rat-race mixer has been alleviated. Moreover, it shows very low conversion loss, high LO-to-RF, LO to intermediate frequency (IF), and 2LO-to-RF port isolations. The measured minimum down conversion loss is 5.8 dB at 13 GHz and remains below 7.65 dB over the 2 GHz RF operational band 12-14 GHz for a fixed IF of 550 MHz. Measured LO-to-RF and LO-to-IF port isolations are better than −40 dB over the entire operational band. The 2LO-to-RF isolation is more than −62 dB which is extremely necessary for a second harmonic mixer where 2LO and RF frequency are close to each other. The input 1-dB compression point is measured to be −1 dBm.

500 GHz CMOS heterodyne imager adopting fourth subharmonic passive mixer

AbstractA 500 GHz heterodyne imager adopting a source‐driven fourth subharmonic single balanced resistive mixer is implemented in 65‐nm CMOS technology. The adopted passive mixer improves the port‐to‐port isolation and minimizes the input matching loss. At an LO power of 5 dBm, the imager achieves a conversion loss and double sideband noise figure of 30.2 dB and 51 dB, respectively, which corresponds to −93 dBm and 15.8 fW/Hz0.5 of sensitivity and the effective noise equivalent power, respectively, assuming a noise bandwidth of 1 kHz. To the best of authors' knowledge, the proposed work is the highest frequency implementation as a CMOS‐based heterodyne imagers adopting resistive mixers.

A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications

This paper presents a millimeter-wave (127 GHz) CMOS transceiver with a digital pre-distortion capable PAM-4 modulator for contactless communications. The transmitter upconverts PAM-4 modulated baseband signals through a free-running 127-GHz oscillator and single-balanced mixer, and it delivers PAM-4 modulated carrier signals to a folded-dipole antenna, which is designed on a FR408HR substrate. The receiver’s low-noise amplifier provides a 10-dB gain, and the self-mixer downconverts carrier-modulated PAM-4 signals to baseband signals without the necessity of carrier synchronization. The PAM-4 modulator pre-distorts the baseband signals and corrects the non-linear characteristics of the transmitter’s upconversion mixer and the receiver’s downconversion self-mixer. Designed and fabricated in a 65-nm CMOS process, the demonstrated system transfers 20 Gb/s of PAM-4 modulated data through a 1-mm air gap and consumes 79.5 mW (transmitter: 50.8 mW and receiver: 28.7 mW) of power under a 1.2-V supply, achieving a 3.98-pJ/bit energy efficiency. The communication distance is extended to 3 cm by inserting a dielectric waveguide between the same transceiver.

Low-Loss SISL Patch-Based Phase Shifters and the Mixer Application

This paper proposes a new class of phase shifters using right-angled triangular patches based on the substrate integrated suspended line (SISL) platform. The reference line and the main line of the phase shifter are both designed in the patch form, which is different from previous works. With the common reference patch fixed, multiway and polyphase SISL phase shifters can be achieved by adjusting the main patch. As demonstration, three SISL patch-based phase shifters with phase shifts of 45°, 60°, and 90°, respectively, have been designed at 24-GHz band and fabricated by the printed circuit board (PCB) process. The radiation loss, conductor loss, and dielectric loss of the proposed patch-based phase shifters have been reduced based on the self-packaged SISL platform, and the measured insertion loss of the SISL phase shifter has a typical value of 0.3 dB at 24-GHz band, which is much smaller as compared with the state of the art. Moreover, the 90° case has been applied to an SISL single-balanced mixer design. Besides the low-loss phase shifter, other components of the mixer are all implemented on the common SISL platform with low loss, and the overall loss of the SISL mixer is very small as compared with the other works. The SISL mixer has a compact size and low conversion loss with a minimum of 5.8 dB at the 24-GHz band.

A 53–67 GHz Low-Noise Mixer-First Receiver Front-End in 65-nm CMOS

In this paper, we present a mixer-first receiver front-end suitable for millimeter wave (mm-wave) applications. The proposed architecture includes a modified single-balanced mixer core with an on-chip balun in order to provide a differential output from an injected single-ended local oscillator signal. The mm-wave active balun incorporates a cascode cross-coupled structure to achieve a high voltage gain with low amplitude and phase imbalance. The inter-stage inductors are utilized to increase the mixer conversion gain (CG). Moreover, by manipulating the transistor body effect in the transconductance stage, the CG and noise figure of the mixer are further improved. The mixer also achieves a high input return loss which makes it suitable for the mixer-first receivers. As a proof-of-concept, a 53–67 GHz mixer with a center intermediate-frequency of 20 GHz is designed and implemented in a 65-nm CMOS process. The mixer achieves a measured peak conversion gain of 12.1 dB and a 1-dB compression point of −5 dBm. Furthermore, the fabricated mixer achieves a minimum double-sideband (DSB) noise figure of 6.5 dB over its bandwidth. The whole chip consumes 11.5 mW from a 1-V supply and excluding the pads occupies 0.27 mm2 of silicon area.

W波段低损耗交叉杆式单平衡混频器

W波段低损耗交叉杆式单平衡混频器

A Highly-Integrated Low-Noise MICS Band Receiver RF Front-End IC with AC-Coupled Current Mirror Amplifier

This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405[Formula: see text]MHz medical implant communications service (MICS) band applications using 0.18-[Formula: see text]m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5[Formula: see text]dB conversion gain, 1.85[Formula: see text]dB noise figure, and IIP3 of [Formula: see text][Formula: see text]dBm while consuming 440[Formula: see text][Formula: see text]W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29[Formula: see text]mm2.

Highly Linear Distributed Mixer in 0.25- $\mu \text{m}$ Enhancement-Mode GaAs pHEMT Technology

This letter presents the design and measured results of novel wideband, highly linear gate-pumped distributed downconverter mixers. The circuit is realized in a 0.25-μm, Enhancement-mode GaAs pseudomorphic High Electron-Mobility Transistor process which requires no negative voltage supply. Two cells with different biases in parallel are used to achieve third-order intermodulation product cancelation. Each cell utilizes the distributed topology to absorb the first-order gate-source capacitances C gs1 . Two mixers are demonstrated: 1) a single-ended (SE) mixer and 2) a single-balanced (SB) mixer. The SE and SB mixers achieve a measured third-order input intercept point above 30 dBm in the RF frequency ranges from 6-26 GHz and 6-20 GHz, respectively. Both mixers show a conversion loss of less than 10 dB. The balanced mixer exhibits more than 30 dB of LO-RF isolation.

Development of Wideband and High IIP3 Millimeter-Wave Mixers

This paper presents the design and development of highly linear, wide bandwidth mixers. We propose a linearization technique that combines the optimum drain bias condition and multiple-gated transistors for resistive mixers. An on-chip three-line edge-coupled Marchand balun is designed to have low phase and amplitude imbalance for canceling out the even order intermodulation products. Two mixer prototypes: a single-balanced (SB) mixer and a double-balanced (DB) mixer are designed to prove the concepts. The experimental results demonstrate that the SB prototype mixer has a measured conversion loss of less than 11 dB and third-order input intercept point (IIP3) range of 27–33 dBm at 15-dBm LO drive from 7 to 34 GHz. The DB mixer exhibits a conversion loss of less than 11 dB and IIP3 range of 31–35 dBm from 7–26 GHz at 17-dBm LO drive. Both prototypes achieve a high port-to-port isolation of over 30 dB within the operation bandwidth. To the best of our knowledge, the mixers have the highest linearity over the widest bandwidth ever reported.

Design of A Compact Single-Balanced Mixer for UWB Applications

The design and implementation aspects of a new single-balanced mixer for ultra-wideband (UWB) applications are presented in this study. The proposed mixer utilizes a miniaturized UWB ring coupler as a balun, consisting of a pair of in-phase and inverted-phase transitional structures. The well-balanced UWB performance of the ring coupler, aside from the optimized diode matching, results in improved conversion loss and inter-port isolations for a wide bandwidth. The size of the implemented single-balanced diode mixer is reduced to about 60% of the area of the conventional single-balanced ring diode mixer. The measured results of the proposed mixer exhibit an average conversion loss of 7.5 dB (minimum 6.7 dB) and a port-to-port isolation of greater than 18 dB over a UWB frequency range of 3.1–10.6 GHz. The measured results agree well with the simulated results.

Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach

Passive mixers have become an essential component of SAW-less communication receivers in the last few years, this has encouraged many researchers to study their impedance characteristics. When observed from the input radio frequency (RF) port of the passive mixer, the impedance exhibits bandpass filtering characteristics centered around the frequency of the local oscillator (LO) signal. The theory of baseband impedance up-conversion is widely accepted in the analysis of passive mixer circuits as well as in describing the origin of this bandpass impedance characteristics. In this paper, we revisit this theory and show that it is not always accurate since it does not account for switching transients. We begin our work by showing that the most commonly used single-balanced mixer is not the right choice for a half-circuit used in analyzing the input impedance of a fully-balanced passive mixer. We propose an alternative half-circuit, and proceed with a novel analysis that accounts for switching transients. This switching-aware analysis allows capturing the switched-capacitor behavior of the passive mixer. We then derive closed-form equations for the mixer impedance using purely-capacitive loads as well as resistive-capacitive (RC) loads. We also discuss the impact of finite LO rise and fall times on the mixer impedance. Simulation results of quadrature passive mixers using ideal and MOSFET switches show very close match with the proposed theoretical analysis.

W-band Downconversion Mixer with Finline Transition for Intelligent Traffic System

A W-band MMIC mixer using 0.15-㎛ T-gate GaAs pHEMT technology is presented. The proposed mixer is designed as a single balanced diode mixer type with schottky barrier diode and implemented with finline transition for 77-㎓ intelligent traffic system(ITS) transceiver(TRx) module. The mixer also includes an IF amplifier to increase a conversion gain, and the waveguide-to-microstrip antipodal finline transition is designed with cosine-squared taper function curve and fabricated with duroid 5880 substrate. The optimized finline transition shows the measured insertion loss of less than 1㏈ and the return loss of higher than 20㏈ for 77㎓. The measured conversion gain of the proposed W-band mixer is 0.3㏈ at LO power of 11㏈m, which satisfies the mixer specification for ITS automotive collision avoidance radar receiver module.

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS gSUBm/SUB-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

A 340-GHz Heterodyne Receiver Front End in 40-nm CMOS for THz Biomedical Imaging Applications

A low-power and high-performance 340-GHz heterodyne receiver front end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this paper. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as –11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital complementary metal–oxide–semiconductor technology. The measured voltage conversion gain is –1.7 dB at 335.8 GHz, while the mixer and the oscillator only consume 0.3 and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.