Sinewave Histogram Test Research Articles

An Improved Sine Wave Histogram Test Method for ADC Characterization

This paper presents a modified version of the sine wave histogram test for analog-to-digital converter (ADC) characterization. To accurately estimate the transition levels, the input signal has to fulfill strict conditions, which are coherent sampling and uniform distribution of the phases. Noncoherent sampling of the sine wave leads to systematic errors in the transition level estimation, while the nonuniform distribution of the phases increases the variance of the results using the original sine wave histogram test method. The source of the errors is the improper modeling of the histogram of the measured signal. This paper shows that the true histogram of the measured sine wave can be reconstructed by estimating the phases of the sampled signal. It is shown that integrating this information into the estimation of the transition levels can significantly decrease the effect of noncoherent sampling, thus the ADC can be characterized accurately even if the conditions are not fulfilled. The proposed method is verified on both simulated and real measurement data.

An Output Response Analyzer Circuit for ADC Built-in Self-Test

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs' parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

A sine-wave histogram-testing structure for analog-to-digital converters (ADCs) is proposed. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the realization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-mum technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.

Simple and Time-Effective Procedure for ADC INL Estimation

This paper deals with a novel testing technique aimed at estimating the accuracy of analog-to-digital converters (ADCs). The main advantage of the proposed approach is the higher testing speed, particularly the ability to achieve an accurate estimate of the low-frequency component (LCF) of the integral nonlinearity (INL) pattern of an ADC in a time that may be even one order of magnitude shorter than that of other standard techniques such as the sine wave histogram test (SHT). The estimation accuracy associated with the testing procedure is determined theoretically and validated by means of simulations and experimental results

Fast estimation of ADC nonlinearities using the Sinewave Histogram Test

The Sinewave Histogram Test (SHT) is a widely used standard technique to estimate the threshold voltages and the Integral NonLinearity (INL) pattern of Analog-to-Digital Converters (ADCs). The main drawback of the SHT is that, for a given target accuracy, the number of test samples as well as the testing time tend to increase exponentially as the resolution of the converter grows. The strategy described in this paper still relies on the SHT, but it enables a major reduction in testing time without affecting estimator accuracy provided that the INL pattern exhibits prevailingly a low code frequency content. This result can be achieved simply by suitably filtering the INL pattern obtained using a standard SHT over a reduced amount of test samples. After being justified theoretically, the proposed solution is validated by means of both simulations and experimental evidences.

Noise sensitivity of the exponential histogram ADC test

This paper deals with some error effects caused by additive noise at analogue-to-digital converters (ADCs) testing based on the histogram method and the exponential shape of input testing stimulus. The histogram method with the exponential stimulus has been an alternative test method for ADC that was developed by the authors of this paper. Here, the theoretical analysis of some errors in estimations of code bin widths and quantisation levels caused by additive input Gaussian noise is performed. The theoretical results are verified by simulations and experimental tests. Finally the noise sensitivity of the exponential histogram test method is compared with the known noise sensitivity of the standardised sinewave histogram test method.

Effective ADC linearity testing using sinewaves

This paper deals with the effectiveness of the sinewave histogram test (SHT) for testing analog-to-digital converters. The implementation is discussed, with respect to the adopted procedures and to the choice of relevant parameters. Some of the published approximations currently limiting the characterization of the test performance are removed. The statistical efficiency of the SHT is evaluated by comparing the associated estimator variance with the corresponding Crame/spl acute/r-Rao lower bound, theoretically derived assuming sinewaves corrupted by Gaussian noise. Finally, both simulation and experimental results are presented to validate the proposed approach.

Statistical efficiency of the ADC sinewave histogram test

This paper presents an analysis of the statistical efficiency of the sinewave histogram test used for estimating the unknown transition levels of an analog-to-digital converter. Accordingly, at first, a closed-form determination of the Cramer-Rao bound is derived under the assumption of a noiseless stimulus signal. Both unbiased and biased versions of the bound are described in order to account for the eventual bias introduced by commonly employed estimators. Then, additive Gaussian noise is assumed, and comments are made about its effects on the maximum achievable accuracy.

ADC sinewave histogram testing with quasi-coherent sampling

In this paper, the accuracy of ADC sinewave histogram testing is analyzed under the assumption of quasicoherent sampling. A bound is derived on the inaccuracy in setting the ratio between sinewave and sampling frequencies, which allows the design of the test for prescribed levels of estimator variance. Detailed proofs and simulation results are presented.

Design of ADC sinewave histogram test

In this paper, sinewave histogram test is considered as a method for the estimation of analog-to-digital converter (ADC) integral nonlinearities. The issues related to the design of test parameters are also discussed with respect to already published directions on this topic. Moreover, particular emphasis is dedicated to the problem of estimating standard uncertainty in accordance with international standards.