SiN Passivation Research Articles

Improved Power Performance and the Mechanism of AlGaN/GaN HEMTs Using Si-Rich SiN/Si3N4 Bilayer Passivation

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Si-rich SiN/Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> bilayer passivation were studied in this article. The use of a Si-rich SiN interlayer leads to improved channel transport property, current collapse, power performance, and temperature-dependent stability. Devices without Si-rich SiN interlayer passivation exhibit an increase in the gate leakage current by over three orders of magnitudes with temperature increasing from 300 to 420 K, leading to an increase in a current collapse from 9.7% to 24.7%, while the devices with Si-rich SiN passivation exhibit a weak temperature dependence of leakage current and a constant current collapse about 5%. Small signal characterization shows that Si-rich SiN passivation results in a remarkable decrease in the effective gate length by ~15% with temperature up to 420 K. At 17 GHz, devices with Si-rich SiN interlayer passivation exhibit an output power density of 7 W/mm and a peak power-added efficiency (PAE) of 56%. The improved power performance of devices using Si-rich SiN interlayer passivation is attributed to the suppressed current collapse and superior device stability under high channel temperature.

8.7 W/mm output power density and 42% power-added-efficiency at 30 GHz for AlGaN/GaN HEMTs using Si-rich SiN passivation interlayer

In this work, high-performance millimeter-wave AlGaN/GaN structures for high-electron-mobility transistors (HEMTs) are presented using a Si-rich SiN passivation layer. The analysis of transient and x-ray photoelectron spectroscopy measurements revealed that the presence of the Si-rich SiN layer leads to a decrease in the deep-level surface traps by mitigating the formation of Ga–O bonds. This results in a suppressed current collapse from 11% to 5% as well as a decreased knee voltage (Vknee). The current gain cutoff frequency and the maximum oscillation frequency of the devices with the Si-rich SiN layer exhibit the values of 74 and 140 GHz, respectively. Moreover, load-pull measurements at 30 GHz show that the devices containing the Si-rich SiN deliver excellent output power density of 8.7 W/mm at Vds = 28 V and high power-added efficiency up to 48% at Vds = 10 V. The enhanced power performance of HEMTs using Si-rich SiN interlayer passivation is attributed to the reduced Vknee, the suppressed current collapse, and the improved drain current.

Investigation of sidewall passivation mechanism of InGaN-based blue microscale light-emitting diodes

Microscale light-emitting diodes (µLEDs) have been extensively employed for solid-state lighting applications. However, the ratio of the sidewall area to the emitting area increases as the pixel size of µLEDs decreases, which increases the non-radiative recombination probability on the sidewall surface and eventually degrades the performance of µLEDs. In this study, we investigate the nature of chemical bonds at the sidewall/passivation layer interface using three passivation materials (SiO2, Al2O3, and Si3N4), to identify the underlying mechanism of passivation and thereby achieve high-performance InGaN-based µLEDs. According to the X-ray photoelectron spectroscopy results, the ratio of GaO bonds on the sidewall/passivation layer interface to GaN bonds varies with the passivation layer (1.1, 1.06, and 0.33 for SiO2, Al2O3, and Si3N4, respectively). This amount is a key factor affecting the passivation and directly influences the µLED performance. The µLED with SiO2 passivation exhibits a 39% higher light output power and 192% higher current density compared to those associated with the µLED with Si3N4 passivation. These results indicate that the suppression of non-radiative defects depends on the chemical states at the sidewall/passivation layer interface. The findings can provide guidance for optimizing the device performance of µLEDs by selecting appropriate passivation layers.

A study of gate recess-width control of InP-based HEMTs by a Si3N4 passivation layer

Recess process for opening a narrow trench in the capping layer for T-shaped gates is one of the most important steps in the fabrication of InP-InAlAs/InGaAs based high electron mobility transistors, since the recessed-width strongly influences the DC/RF performances of the devices. Conventional chemical wet etch fails to well control the recess-width and its uniformity, leaving the seemingly small issue still rarely addressed so far. This work quantitatively analyzed the relationship between the recess-width and the DC/RF properties of the device by numerical simulations. To enhance the controllability of the recess-width, a 20-nm thick Si3N4 passivation layer pre-grown on the top of the capping layer was proposed. Careful comparisons of the recess-width as well as the device property with and without the passivation layer was carried out. Our results from both experiments and simulations indicate that it is promisingly feasible to control the recess-width to the desired scale by chemical wet etch when a dielectric layer such as Si3N4 is applied to protect the InGaAs capping layer from being over recessed, leading to enhanced device performance. With such an additional Si3N4 passivation layer, it is expected that the manufacturing yield of the InP-based high electron mobility transistors should be significantly enhanced with improved device performances.

A 0.43 V/90 nA/mm Lateral AlGaN/GaN Schottky Barrier Diode With Plasma-Free Groove Anode Technique

In this letter, high-performance AlGaN/GaN Schottky barrier diodes (SBDs) with a great balance between forward and reverse characteristics are demonstrated. Benefiting from a plasma-free, low-damaged wet etching technique of an AlGaN layer at the anode region and low work-function tungsten (W) as the anode, lateral GaN SBDs with a low turn-on voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{{\mathrm {T}}}$ </tex-math></inline-formula>) of 0.43 V and a low reverse current (<inline-formula> <tex-math notation="LaTeX">$\text{I}_{{\mathrm {R}}}$ </tex-math></inline-formula>) of 90 nA/mm are obtained. Meanwhile, owing to the flattened self-terminated etching surface and the assistance of SiN passivation grown by low-pressure chemical vapor deposition, a high breakdown voltage of 1.83 kV and a power figure-of-merit (FOM) of 1.20 GW/cm² are achieved for the fabricated GaN SBD with a spatial distance (<inline-formula> <tex-math notation="LaTeX">$\text{L}_{{\mathrm {AC}}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math notation="LaTeX">$15 ~\mu \text{m}$ </tex-math></inline-formula> from cathode to anode. The lateral GaN SBD fabricated with the optimized wet etching technique shows great potential for next-generation power electronics.

Optimized Device Geometry of Normally-On Field-Plate AlGaN/GaN High Electron Mobility Transistors for High Breakdown Performance Using TCAD Simulation

This study presents the optimization of the lateral device geometry and thickness of the channel and barrier layers of AlGaN/GaN high electron mobility transistors (HEMTs) for the enhancement of breakdown voltage (VBR) characteristics using a TCAD simulation. The effect of device geometry on the device performance was explored by varying the device design parameters, such as the field plate length (LFP), gate-to-drain length (LGD), gate-to-source length (LGS), gate length (LG), thickness of the Si3N4 passivation layer (Tox), thickness of the GaN channel (Tch), and AlGaN barrier (Tbarrier). The VBR was estimated from the off-state drain current versus the drain voltage (IDS–VDS) curve, and it exhibited a strong dependence on the length and thickness of the parameters. The optimum values of VBR for all the device’s geometrical parameters were evaluated, based on which, an optimized device geometry of the field-plated AlGaN/GaN HEMT structure was proposed. The optimized AlGaN/GaN HEMT structure exhibited VBR = 970 V at IGS = 0.14 A/mm, which was considerably higher than the results obtained in previous studies. The results obtained in this study could provide vital information for the selection of the device geometry for the implementation of HEMT structures.

Influence of AlN passivation on thermal performance of AlGaN/GaN high-electron mobility transistors on sapphire substrate: A simulation study

This work describes the self-heating effects on the behavior of AlGaN/GaN-based high-electron Mobility Transistors (HEMTs), which are grownon Sapphire substrate, using electro-thermal TCAD simulations. The proposed device, passivated with AlN/SiN, demonstrates more excellent thermal performance than the conventional one with SiN passivation due to the introduction of additional AlN on top of the device, which acts as a heat spreader. The electro-thermal simulations have carried out for different AlN thicknesses (0 µm to 25 µm), and the device with 5 µm AlN shows better performance compared to others. The proposed AlN/SiN stacked passivation HEMT shows a comparatively small lattice temperature of 418 K, whereas the conventional HEMT with SiN passivation shows 578 K. All the devices (gate length, LG = 1 µm) switch from OFF- to ON-states using the voltage, VGS from −10 V to 0 V with fixed bias, VDS = 5 V. The values of saturation drain current density (IDSS) and transconductance (gm) are 0.7 A/mm and 173 mS/mm for the proposed HEMT with 5 µm AlN considering the thermal simulation model. In contrast, the conventional device demonstrates those of 0.42 A/mm and 109 mS/mm, respectively. The ∼ 0.32 A/mm of drain current recover for the proposed device with 5 µm AlN from a conventional device because of the reduction of self-heating effects. Our study reveals that the AlN/SiN passivation HEMTs are a promising technology for high-power switching and microwave applications without significant reduction in device performance at high drain bias.

Impact of SiN passivation film stress on electroluminescence characteristics of AlGaN/GaN high-electron-mobility transistors

This letter reports an impact of SiN film stress on electroluminescence (EL) of AlGaN/GaN HEMTs. The EL color of HEMTs turned from high-intensity white to low-intensity red, as the SiN film stress was increased from −24.2 (compressive) to +11.5 MPa (tensile). The weak reddish EL from the HEMT with a film stress of +11.5 MPa turned bright whitish when a drain-to-source voltage (V ds) was increased. A transient I d response after biasing stress revealed that severe current collapse emerged in the HEMT with a film stress of −24.2 MPa. In addition, the current collapse in HEMTs increased with the increased V ds.

Performance improvement of Al0.3Ga0.7N/AlN/GaN HEMTs using Nitrogen pre-treated Si3N4 passivation

In the present study, new process of N2 pre-treated (NP) Si3N4 passivation on Al0.3Ga0.7N/AlN/GaN HEMTs (High Electron Mobility Transistors)has been developed and its impact on DC and RF performance of HEMTs has been investigated. Additionaly, this study reveals the beneficial effects of NP passivation on RF performance in comparison to w/o NP passivation. The physical role of NP passivation is explained through extraction of small signal model parameters.NP Si3N4 passivation layer was deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) technique and was analysed using analytical techniques like X-ray Photoelectron Spectroscopy (XPS), High Resolution X-Ray Diffraction (HR-XRD), Ellipsometry & Fourier Transform Infrared Spectroscopy (FTIR). After NP passivation, devices exhibited better DC/RF characteristics. For a device, with gate-length of 0.25 μm, drain current density (Idss) increased from 747 to 876 mA/mm and the peak transconductance(gm) increased from 192 to 236 mS/mm.The cut-off frequency (Ft) increased from 28.6 to 49.5GHz, maximum frequency oscillation (Fmax)increased from 27.2 to 42.5GHz &maximum available gain @ 8GHz increased from 11 dB to 15 dB for w/o NP passivation and with NP passivation respectively.

The effect of barrier layers on 2D electron effective mass in Al0.3Ga0.7N/AlN/GaN heterostructures

The Shubnikov de Haas (SdH) effect measurements have been performed to evaluate the influence of Si3N4 passivation, a spacer layer, and Si-doped barrier layer on the electronic transport parameters of two-dimensional (2D) electrons in Al0.3Ga0.7N/AlN/GaN heterostructures under temperatures from 1.8 K to 40 K and at a magnetic field up to 11 T. The 2D electron effective mass (m*), 2D carrier density (N 2D), the difference between Fermi level and subband energy levels (E F − E 1), quantum lifetime (τ q) are determined by analyzing SdH oscillations. Although investigated samples with equal 2D electron density are examined, the effective mass values of 2D electrons are deduced within the range of (0.16 ± 0.005)m 0 and (0.23 ± 0.005)m 0. Results reveal that passivation, a spacer layer, and doping affect 2D electron effective mass. Furthermore, the dominant scattering mechanisms that limited electron transport is determined as a long-range scattering for all investigated sample. The results obtained provide information for the high-performance device application of these samples.

Investigation of the passivation-induced VTH shift in p-GaN HEMTs with Au-free gate-first process

In this work, we observe the distinct VTH characteristics in the Au-free gate-first processing p-GaN/AlGaN/GaN HEMTs with two commonly used passivation layers, i.e., SiN and SiO2. The lower incorporated H was found in the p-GaN/AlGaN/GaN heterostructure with higher activation anneal temperature (i.e., 700 °C). Furthermore, Photoluminescence (PL) spectrum demonstrates a higher blue luminescence (BL) intensity after higher annealing treatment. The X-ray photoelectron spectroscopy (XPS) spectrum near valence band edge depicts a similar valence band maximum (VBM) characteristic, by means no impact on p-GaN surface bending by using distinct thermal treatment. The device with SiN shows a depletion-mode (D-mode) characteristic (VTH ~ -5 V) whereas the device with SiO2 passivation exhibits an enhancement-mode (E-mode) characteristic (VTH ~ +0.7 V). Moreover, Transmission Line Model (TLM) devices are fabricated to investigate the effects of the passivation on two-dimensional electron gas (2DEG) in p-GaN/AlGaN/GaN stack. The results indicate that a low Rsh is obtained while passivating device surface with SiN layer, suggesting that 2DEG is present, which is most probably due to an unfunctional p-GaN layer. The secondary ion mass spectrometry (SIMS) results indicate a high hydrogen intensity in the p-GaN/AlGaN/GaN stack with a SiN passivation layer. Thus, the p-GaN deactivation process that correlates to the formation of complex MgH after SiN passivation is proposed to explain the D-mode characteristic in the device with a SiN passivation layer.

Passivation-layer thickness and field-plate optimization to obtain high breakdown voltage in AlGaN/GaN HEMTs with short gate-to-drain distance

A two-dimensional analysis of the off-state breakdown characteristics in field-plate AlGaN/GaN HEMTs is performed. The gate-to-drain distance is 1.5 μm, and the parameters are the SiN passivation-layer thickness d and the field-plate length LFP. For a moderate d of 0.1 μm, the breakdown voltage Vbr increases with LFP, and takes an maximum value (~400 V) around LFP = 0.3 μm, and decreases when LFP becomes even longer. This decrease is attributed to the fact that the drain voltage is almost applied along the region between the field plate and the drain. For thin d ≤ 0.03 μm, Vbr becomes relatively low (≤150 V) when LFP becomes long (≥ 0.6 μm). This is attributed to the fact that when d is very thin, the field plate acts like a gate electrode. When d is relatively thick (≥0.3 μm), Vbr decreases at LFP = 0.3 μm as compared to the case of d = 0.1 μm, and it decreases to 250 V at d = 0.5 μm. This is because the field-plate effects become weak for thick d. The optimum thickness of the SiN passivation layer is approximately 0.1–0.2 μm and Vbr peaks at approximately 400 V when LFP = 0.3 μm. The novelty of this paper is to show the dependence of Vbr on the passivation-layer thickness d and the field-plate length LFP when the gate-drain distance is short.

Improvement in Electrical and 2DEG Properties of Al0.26Ga0.74N|GaN|Si HEMTs

Improving material quality is essential for obtaining a high-power device. Surface trapping effects have been present in all HEMT devices, and have significantly impacted the problem of drain-current collapse. In this paper, performance of intentionally non-doped AlGaN|GaN|Si (HEMTs) before and after passivation with SiO2|SiN is investigated. Capacitance-voltage at various temperatures (C–V–T), a drain current–voltage at various gate voltages (Ids–Vds–Vgs), the gate leakage current with various temperatures (Igs–Vgs–T), and the maximum extrinsic transconductance Gmax are measured; all of these measurements show the impact of SiO2|SiN passivation on the performances of AlGaN|GaN|Si HEMTs.

The dual-suppression of peak electric field in AlGaN/GaN HEMT with sandwich structure

To improve the power and RF performance of the high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructure junction, in this paper, a sandwich structure consisting of gate field plate, SiN passivation layer, and notch structure is proposed. The notch structure at the AlGaN barrier layer between the gate and drain is formed by the Inductively Coupled Plasma etching system (ICP), and the notch has a depth of 15 nm. The dual-suppression of the peak electric field contributes to the breakdown voltage of 91 V, which is a 152.8% improvement compared with the conventional HEMT. The decrease of C gd due to increase of distance between the gate electrode and the lower surface of the depletion layer contributes to the cut-off frequency of 24.1 GHz, which is an 8% improvement. Thus, this composite-structure HEMT has a JFOM of 2.2 THz V, it is an 84.6% improvement compared with the conventional gate field plate HEMT. A well suppression of current collapse is also achieved. It has potential in high power and RF applications. • The Sandwich structure manufacturing process is compatible with the conventional process for AlGaN/GaN HEMTs. • The Sandwich structure has a good suppression on the peak electric field, and it can decrease the capacitance between the gate and drain. • The Sandwich structure not only improves the breakdown characteristic but also improves the cut-off frequency characteristics. • The manufacturing process of the notch structure at AlGaN barrier layer does not cause the surface damage.

Investigating the Current Collapse Mechanisms of p-GaN Gate HEMTs by Different Passivation Dielectrics

In this letter, the dynamic R on degradation mechanisms of the p-GaN gate HEMTs induced by off -state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including V TH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The V TH positive shift diminishes the drain current by shrinking the overdrive V GS, which however, can be compensated by a higher V GS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and V TH shift have a very slow recovery process.

Investigation of Influence of SiN and SiO2 Passivation in Gate Field Plate Double Heterojunction Al0.3Ga0.7N/GaN/Al0.04Ga0.96N High Electron Mobility Transistors

This research article reports the operational characteristics of gate field plate double heterojunction (DH) high electron mobility transistors (HEMTs) using SiN (SiO2) passivation techniques. The proposed HEMT exhibits 496 (292) V breakdown voltage (VBR) for LG (gate-length) = 0.25 μm, LGD (drain-gate distance) = 3.2 μm and 1 μm field plate length HEMT. The n + GaN source/drain regions with SiN (SiO2) passivation AlGaN/GaN/AlGaN HEMT delivered 1.4 (1.3) A/mm peak drain current density (Ids), 540 (550) mS/mm gm (transconductance), fT/fMAX of 54/198 (62/252) GHz, and the sub-threshold drain leakage current of 4 × 10−13 (1 × 10−11) A/mm. The high Johnson figure of merit (JFoM = fT × VBR) of 28.76 (19.27) THz.V and excellent VBR × fMAX product of 90.27 (73.29) THz.V demonstrates the great potential of the optimized gate field plate DH-HEMTs structure for U and V band high power microwave electronics.

A Study on the Optimized Ohmic Contact Process of AlGaN/GaN-Si MIS-HEMTs

AlGaN/GaN-Si based MIS-HEMTs are considered as the popular candidates for application in the 5G communication system due to their competitive characteristics and low cost. Ohmic contact, as an important fabrication process, significantly affects the performance of the device. In this study, the ohmic contact process, including the SiN passivation layer etching, surface treatment, and barrier layer etching, was studied in detail in order to effectively optimize the device performance. It is observed that the sample with the SiN passivation layer etched by the magnetic neutral loop discharge (NLD) resulted in a lower contact resistance as compared to the reaction ion etching (RIE). The sample surface treated with the O plasma and pickled in the HCl:H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O = 1:10 liquid could effectively remove the pollutants and oxides from the surface, thus, correspondingly presenting a lower ohmic contact resistance as compared to the N2 plasma. Meanwhile, an optimum etching depth was developed with the ICP process for 6 min with an etching speed of 1.6 nm/min. A contact resistance of 0.76 Ω · mm and square resistance of 274.63 ohm/sq were observed under the above-mentioned optimized ohmic contact process. The AlGaN/GaN-Si MIS-HEMT with gate length of 0.5 μm, gate-source space of 1 μm, gate-drain space of 2.5 μm, and gate width of 100 μm was fabricated using the optimized process. A saturation current density of 794.30 mA/mm and the maximum transconductance of 16.86 mS were observed. The findings in this study provide the experimental basis for the manufacturing of AlGaN/GaN-Si based MIS-HEMTs for RF applications.

Breakdown voltage enhancement of gate field plate Al0.295Ga0.705N/GaN HEMTs

ABSTRACT The breakdown characteristics of Al0.295Ga0.705N/GaN high electron mobility transistors (HEMTs) have been studied with Al0.04Ga0.96N blocking layer and gate field plate technique. LG = 0.4 µm HEMT with 0.8 µm SiN passivation shows 2.16 A/mm drain current (IDSmax) at gate voltage, VGS = 2 V. The breakdown voltage of the HEMT is investigated for various field plate length (LFP = 1, 1.25, 1.5, 1.75, and 2 µm) and the device shows the maximum VBR of 871 V and JFoM of 34.88 THz-V for a gate-field plate length (LFP) = 1.75 µm. The device performance has also been studied for the high-k passivation HfO2 layer with an identical structure. The device shows an enhanced VBR of 912 V with JFoM of 25.53 THz-V. These results indicate that the proposed Al0.295Ga0.705N/GaN/Al0.04Ga0.96N double heterojunction (DH) HEMTs are suitable devices for next-generation high-power microwave applications.

A CMOS Test Chip With Simple Post-Processing Steps for Dry Characterization of ISFET Arrays

ISFETs (ion sensitive field effect transistors) are ion solid-state sensors based on MOSFETs (metal oxide semiconductor field effect transistors) applied in many areas including ion imaging, detection of viruses and bacteria and DNA sequencing. ISFETs implemented in standard CMOS technology adopt the inherent Si3N4 passivation as the sensing layer, and benefit from a high integration level with no need of post-processing steps. However, this implementation is associated with non-idealities such as output temporal drift, capacitive attenuation of the input signal and random offsets in the threshold voltage due to trapped charges. Most of these non-idealities, which require better understanding, are characterized through biasing a reference electrode immersed in a solution in contact with the passivation layer. To remove electrochemical effects from the measurements, this paper proposes a dry test where the wet test setup is replaced with a sputtered gold thin film that provides electrical contact with the ISFETs. Dry tests were performed in arrays of n-ISFETs and p-ISFETs from chips fabricated in a standard 180 nm high voltage CMOS technology. The intra-die threshold voltages of the n-ISFETs and p-ISFETs presented, on average, similar offsets, but their die-to-die fluctuation was high. Wet tests on an n-ISFET and a p-ISFET of two non-metalized chips indicated sensitivities of 38 mV/pH and 46 mV/pH, respectively. The dry test introduced herein allows the electrical parameters of ISFETs to be determined without the interference of chemical contributions as well as the charges trapped in the passivation layer to be estimated.

The role of SiN/GaN cap interface charge and GaN cap layer to achieve enhancement mode GaN MIS-HEMT operation

The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to measured I-V characteristics of the 1 μm gate length GaN MIS-HEMT with the 2 nm thick GaN cap. A good agreement at low and high drain voltages (VDS=1 V and 5 V) between simulations and measurements is achieved by using a quantum-corrected drift-diffusion transport model. The enhancement mode GaN MIS-HEMT with a GaN cap thickness of 35 nm achieves Vth = + 0.5 V thanks to positive interface traps occurring between the SiN passivation layer and the GaN cap as reported experimentally. The simulations indicate that a parasitic channel is created at the interface between the SiN layer and the 35 nm GaN cap. Our study also shows an increase in the breakdown voltage from 100 V to 870 V when a thickness of the GaN cap layer increases from 15 nm to 35 nm.