Simulation Of Logic Circuits Research Articles

Sequential and parallel strategies for the demand-driven simulation of logic circuits

This paper examines methods for the simulation of digital logic circuits using a demand-driven schedule of evaluation. Demand-driven evaluation, in contrast with conventional event-driven and related methods, enables the exploitation of lazy evaluation to reduce simulation time. This potential is maximised by an effective ordering of demands in the evaluation schedule. Optimal ordering strategies are described, for both sequential and parallel evaluation cases, and a near-optimal heuristic strategy is identified for two processor evaluation. Simulation results are presented which demonstrate the effectiveness of the method and strategies employed.

A super parallel sorter using a binary neural network with AND-OR synaptic connections

This paper presents an ultra-high-speed sorter based upon a simplified parallel sorting algorithm using a binary neural network which consists both of binary neurons and of AND-OR synaptic connections to solve sorting problems at two and only two clock cycles. Our simplified algorithm is based on the super parallel sorting algorithm proposed by Takefuji and Lee. Nevertheless, our algorithm does not need any adders, while Takefuji's algorithm needs n×(n−1) analog adders of which each has multiple input ports. For an example of the simplified parallel sorter, a hardware design and its implementation will be introduced in this paper, which performs a sorting operation at two clock cycles. Both results of a logic circuit simulation and of an algorithm simulation show the justice of our hardware implementation even if in the practical size of the problem.

Edge: An extendible graph editor

EDGE is an editor kernel for the direct and visual manipulation of graphs. The kernel can be adapted quickly to diverse applications based on graphs, such as PERT chart editing, directory browsing, call graph display, logic circuit simulation or configuration visualization. EDGE provides potential solutions to the following general problems faced by any graph editor. (1) Automatic graph layout: how can application-specific layout requirements, individual preferences, and layout stability be integrated with automatic layout algorithms? EDGE solves this problem with a novel algorithm that is based on layout constraints. (2) Graph abstraction: how can users deal with large graphs containing hundreds of nodes and edges, and thousands of edge crossings? EDGE can reduce the apparent complexity with subgraph abstractions and a novel clustering technique called edge concentration. (3) Adaptability: how should the editor kernel be structured to be adaptable to various applications? EDGE uses a special graph representation language for specifying visual appearance and the inheritance mechanism of C++ to achieve extendibility. (4) Persistence of graphs: how can the graph structures produced by the editor be kept in long-term storage, especially if the node and edge data structures have been extended for a particular application? Our approach uses a standardized, external format for graphs and handles extensions with program generator technology: the I/O routines for reading and writing extended node and edge data structures are produced automatically from the declarations of these data structures. This paper describes EDGE and presents details of the above solutions.

MAN‐YO: Mixed level parallel logic simulation engine

AbstractMAN‐YO is a special‐purpose parallel computing machine being developed for logic circuit design and simulation. It uses dedicated hardware to increase the speed of gate‐level simulation, and a combination of dedicated microprograms and processors for functional level simulation. Furthermore, a multiprocessor architecture, interconnected by a loop‐network, is used to provide concurrent processing capability for high performance, multilevel logic simulation. Experiments were conducted to assess the performance of the functional level simulation.

Dynamic storage allocation: Experiments using the c language

AbstractThe paper discusses the problem of dynamic storage allocation (DSA) using C in a VMS environment. The problem is studied in a specific context, i.e. fault simulation of logic circuits. However, owing to its intrinsic generality, the adopted solution can be effectively applied to a large number of similar situations. It is shown how the use of standard C‐functions for dynamic memory allocation result unacceptable for efficiency reasons and different implementation strategies to solve the problem are presented.

Parallel Fault Simulation Using Distributed Processing*

This paper presents a method of performing fault simulation of digital logic circuits using a special-purpose computer with distributed processing. The architecture for true value simulation presented in an earlier paper can also be used for parallel fault simulation. The special-purpose computer consists of inexpensive microprocessors interconnected by either a time-shared parallel bus or a cross-point matrix. The cross-point matrix provides higher performance than the time-shared parallel bus. The performance of the proposed simulator is better by over two orders of magnitude than traditional logic fault simulation performed on a general-purpose computer. The power of the simulator is proportional to the number of microprocessors over a certain range.

Time response of small capacitance tunnel junctions and the simulation of fast logic circuits

A simulation method of small time constant Josephson tunnel junctions is developped. It is based on a first order series expansion of the time dependent Josephson current given by the microscopic BCS theory. The method is well adapted to the switching dynamic of logic gates when the RSJC model lacks of accuracy, has a comparable efficiency both in computer time and memory space. The scaling down of resistively coupled logic gates is presented among the illustrations.

Part 1: Logic circuit simulation

As digital integrated-circuits become more complex, the designer cannot rely on breadboarding but must use a digital computer for circuit simulation to verify correctness of the design. Top-down design, using many simulation levels in a hierarchical structure, is needed for complex systems. Simulation can be used at the Circuit, Logic, RTL, ISP, or Systems Analysis level. To verify the design of a circuit, True-Value Simulation is used. Fault Simulation must be used to determine the proper sequence of test signals used in circuit acceptance after fabrication. A general overview of simulation is given in this first part. A subsequent article will contain a description of a general purpose logic simulation with circuit examples.

LAMP: Logic-Circuit Simulators

The algorithms used for logic-circuit simulation in the Logic Analyzer for Maintenance Planning (LAMP) system are described. Several simulators are available to allow a cost-effective tradeoff between simulation cost and the level of detail needed for a particular application. The true value simulator provides efficient simulation of fault-free logic circuits. Two fault simulators simulate the classical stuck-at faults as well as shorted-gate-output faults. Hyperactive faults, those faults which cause an inordinate amount of simulation activity, are discussed along with their impact on simulation time. A four-value simulation logic is described which simplifies circuit initialization procedures.