Leakage Current Simulation Research Articles

Quasi-3D TCAD modeling of STI radiation-induced leakage currents in SOI MOSFET structure

Quasi-3D model for calculation of radiation leakage currents in modern submicron Silicon-on-Insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) structures is proposed. The solution of a complex 3-dimensional problem is reduced to solving two tasks: 2D modeling of the traditional MOSFET cross-section and 3D modeling of the side parasitic transistor. The radiation-induced leakage current simulation in the 0.35 μm SOI MOSFET structure with taking account ionizing radiation with a dose of up to 500 krad was simulated. The results of the simulation show that in comparison with the traditional fully 3D modeling, which requires 11 hours of computer time, the computer time for the IdVg characteristic was reduced to 71 minutes (i.e. the computer time decreased by 9 times).

Drift-diffusion simulation of leakage currents in unintentionally doped organic semiconductors with non-uniform interfaces

Organic electronic devices frequently employ intrinsic semiconductors as active layer. The choice of different materials for the charge injecting and extracting interfaces gives rise to a finite contact potential. Injection of holes against the built-in electrical field results in a diffusion-limited exponential current–voltage characteristic at low bias. Leakage currents, however, seek paths with preferable negative built-in voltages arising from non-uniform interface properties. Along such paths holes are spilled into the intrinsic layer from the charge extracting contact whose Fermi energy is pinned in the lower half of the semiconductor’s band gap. We show here that the drift movement of holes opposed by diffusion can lead to a sublinear increase in the injected current with voltage. Charge injection is assisted by a built-in electrical field, depending mainly on the dopant density and the potential barrier at the injecting contact. Variability of these important properties can arise unintentionally, e.g., due to ambient processing, and low bias currents can serve as simple monitor. As a model system, measured current voltage characteristics of ambient processed poly(3-hexylthiophene-2,5-diyl) (P3HT) films are compared to numeric simulations solving the coupled nonlinear Poisson and drift-diffusion differential equations illustrating the basic principle.

A comprehensive study of the impact of dislocation loops on leakage currents in Si shallow junction devices

In this work, the electrical properties of dislocation loops and their role in the generation of leakage currents in p-n or Schottky junctions were investigated both experimentally and through simulations. Deep Level Transient Spectroscopy (DLTS) reveals that the implantation of silicon with 2 × 1015 Ge cm−2 and annealing between 1000 °C and 1100 °C introduced two broad electron levels EC − 0.38 eV and EC − 0.29 eV in n-type samples and a single broad hole trap EV + 0.25 eV in the p-type samples. These trap levels are related to the extended defects (dislocation loops) formed during annealing. Dislocation loops are responsible for the significant increase of leakage currents which are attributed to the same energy levels. The comparison between structural defect parameters and electrical defect concentrations indicates that atoms located on the loop perimeter are the likely sources of the measured DLTS signals. The combined use of defect models and recently developed DLTS simulation allows reducing the number of assumptions and fitting parameters needed for the simulation of leakage currents, therefore improving their predictability. It is found that simulations based on the coupled-defect-levels model reproduce well the measured leakage current values and their field dependence behaviour, indicating that leakage currents can be successfully simulated on the exclusive basis of the experimentally observed energy levels.

Conduction barrier offset engineering for DRAM capacitor scaling

DRAM capacitors are reaching the scaling limit and new approaches are necessary to enable further reduction of the physical thickness of the capacitor dielectric. The conduction band offset (CBO) of a platinum noble metal electrode on atomic layer deposited ZrO2/Al2O3/ZrO2 is evaluated and compared to a titanium nitride electrode. Internal Photo Emission Spectroscopy and Photoconductivity measurement are used to estimate the barrier height and band gap, respectively. The barrier height difference between the two electrodes is evaluated in comparison with a previously reported model. Finally, the impact of an increased barrier height on dielectric scaling will be discussed based on a leakage current simulation of a ZrO2 capacitor.

Leakage Current Simulation of Insulating Thin Film Irradiated by a Nonpenetrating Electron Beam

We perform numerical simulations of the leakage current characteristics of an insulating thin film of SiO2 negatively charged by a low-energy nonpenetrating focused electron beam. For the formation of leakage current, electrons are demonstrated to turn from diffusion to drift after clearing the minimum potential barrier due to electron-hole separation. In the equilibrium state, the leakage current increases approximately linearly with the increasing primary beam current and energy. It also increases with the increasing film thickness and trap density, and with the decreasing electron mobility, in which the film thickness has a greater influence. Validated by some existing experiments, the simulation results provide a new perspective for the negative charging effects of insulating samples due to the low-energy focused electron beam.

Electrical equivalent circuit of ceramic insulators with RTV silicone rubber coating and computer simulation of leakage currents

During operation, high voltage insulators may severe a certain degree of pollution which may reduce their performances. RTV silicone rubber coating was proposed to improve the performances of outdo...

Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging

This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5 pF capacitance and 240 Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.

Simulation of leakage currents in (Ba,Sr)TiO3 thin films with extracted charge profile

Though many researchers have realized the importance of charge density and distribution to the leakage currents of (Ba,Sr)TiO3 (BST) thin films, till now, there has been no effective method of determining the charge profile of high-permittivity thin films directly. Most studies of the leakage currents of BST thin films are simply based on the assumption that the charge density is identical throughout the films. This is not an exact way to understand the nature of leakage currents. In this paper, we have extracted the charge profile from capacitance–voltage measurements and then used the combined model of thermionic emission and drift diffusion to simulate the leakage currents. Using the extracted charge profile, the thermionic emission and drift diffusion model, with almost all the parameters consistent with separate measurements or theoretical results, can fit the leakage characteristic of the BST film very well at medium–high fields and sufficiently high temperature. Based on the simulation results, the leakage conduction mechanism is determined reliably.

Statistical simulation of leakage currents in mos and flash memory devices with a new multiphonon trap-assisted tunneling model

A new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multiphonon trap-assisted tunneling as conduction mechanism, calculates the total leakage current summing the contributions of the percolation paths formed by one or more aligned traps. Spatial positions and energetic levels of traps have been randomly generated within the oxide by a random number generator which has been integrated into the model. Using this model, statistical simulations of leakage currents measured from both MOS and Flash EEPROM memory tunnel oxides have been carried out. In this way, experimental leakage current distributions can be directly reproduced, thus opening a wide range of useful applications in MOS and Flash EEPROM memory reliability prediction.

DISCRETIZATION METHODS AND PHYSICAL MODELS FOR SIMULATING LEAKAGE CURRENTS IN SEMICONDUCTOR DEVICES WITH APPLICATION TO MODELING TRENCH‐DRAM CELLS

Challenges to a robust and accurate implementation of electric‐field‐enhanccd thermal‐generation mechanisms in a drift‐diffusion‐based semiconductor‐device simulation code are discussed and solutions proposed. The implementation of the physical models and associated numerical methods is applied to the simulation of leakage currents in trench‐DRAM cells.