Simplified Successive Cancellation Research Articles

High-Throughput Polar Code Decoders with Information Bottleneck Quantization.

In digital baseband processing, the forward error correction (FEC) unit belongs to the most demanding components in terms of computational complexity and power consumption. Hence, efficient implementation of FEC decoders is crucial for next-generation mobile broadband standards and an ongoing research topic. Quantization has a significant impact on the decoder area, power consumption and throughput. Thus, lower bit widths are preferred for efficient implementations but degrade the error correction capability. To address this issue, a non-uniform quantization based on the Information Bottleneck (IB) method is proposed that enables a low bit width while maintaining the essential information. Many investigations on the use of the IB method for Low-density parity-check code) LDPC decoders exist and have shown its advantages from an implementation perspective. However, for polar code decoder implementations, there exists only one publication that is not based on the state-of-the-art Fast Simplified Successive-Cancellation (Fast-SSC) decoding algorithm, and only synthesis implementation results without energy estimation are shown. In contrast, our paper presents several optimized Fast-SSC polar code decoder implementations using IB-based quantization with placement and routing results using advanced 12 nm FinFET technology. Gains of up to 16% in area and 13% in energy efficiency are achieved with IB-based quantization at a Frame Error Rate (FER) of 10-7 and a polar code of N=1024,R=0.5 compared to state-of-the-art decoders.

Cyclic redundancy check-aided successive cancellation-based polar decoders

<span>Research on channel coding for network transmission using polar codes has produced excellent results. By removing error redundancy from the decoding process, cyclic redundancy check (CRC) is frequently used by researchers to increase a system’s performance. In prior research, the application of decoder algorithms for polar codes was examined but not thoroughly compared. For the general capabilities of the previously proposed algorithms to be ascertained, it is crucial to analyze the employment of polar decoders especially successive cancellation (SC)-based polar decoders and the use of CRC in additive white gaussian noise (AWGN). Hence, this paper analyzes the performance of CRC with SC-based polar decoders in AWGN. In the simulation setup, (256,128) polar codes and CRCs with three-bit sizes (6, 8 and 11) were utilized. SC-based polar decoders, such as SC, soft-output cancellation, SC list (SCL) and simplified SC, were applied at the decoder part. The outcomes show that CRC-aided SC-based polar decoders reduced redundancy error. Among all the decoders, the SCL decoder with 11-bits CRC performed well when the normalized signal-to-noise ratio was high. Based on the analysis, removing errors at the highest level is possible using a suitable CRC size for SC-based polar decoders.</span>

Decoding of the extended Golay code by the simplified successive-cancellation list decoder adapted to multi-kernel polar codes

This paper describes an adaptation of a polar code decoding technique in favor of the extended Golay code. Based on the bridge provided by a permutation matrix between the code words of these two classes of codes, the Golay code can be decoded by any polar code technique. Contrary to the successive-cancellation list technique which is characterized by a serial estimation of the bits, we propose in this work an adaptation of the simplified successive-cancellation list technique to polar codes equivalent to the Golay code. The simulations have achieved the performance of a maximum likelihood decoding, with the low decoding complexity of polar codes, compared to one of the universal decoders of linear codes most known in the literature.

Generalized Constituent Nodes for Simplified Successive-Cancellation Decoding of Multi-Kernel Polar Codes

The decoding latency of the successive-cancellation decoder for polar codes is of great importance in its practical applications, and it can be reduced by implementing multi-bit decision decoders in the constituent nodes of the decoding tree. In this letter, we develop a matrix analysis method to analyze the corresponding parity submatrix of the decoding tree’s internal node. Two generalized constituent nodes are presented for the fast simplified successive-cancellation (fast-SSC) decoding of linear kernels-mixed multi-kernel polar codes. Results show that the proposed method achieves latency reduction and preserves the error-correction performance.

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing

Benefiting for its capacity-achieving property, the polar codes have attracted wide attention in various forward error correction (FEC) codes. Although Successive-Cancellation (SC) decoders have low hardware complexity, their limited thoughput leads to low hardware efficiency. In this paper, two novel processing elements (PE) units for SC decoders are proposed by the reconstruction of key functions. Approximate comparator and adder-subtractor are developed in the proposed PEs to further enhance the hardware efficiency of the SC decoders with neglectable bit error rate (BER) performance degradation. The designs are implemented and evaluated on 28nm CMOS technology. Simulation results indicate that the area efficiency of two designs are 17.758r <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {Gb/s/mm^{2}}$ </tex-math></inline-formula> and 14.416r <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {Gb/s/mm^{2}}$ </tex-math></inline-formula> with 1024-bit code length and the code rate r, which are 26.7% and 9.7% better than the state-of-the-art SC implementations. Moreover, the low complexity Fast Simplified SC (Fast-SSC) decoder implemented with proposed approximate PEs has 60.3% area efficiency improvement than the prior Fast-SSC decoders with equivalent BER performance.

Single parity check node adapted to polar codes with dynamic frozen bit equivalent to binary linear block codes

&lt;span lang="EN-US"&gt;In the context of decoding binary linear block codes by polar code decoding techniques, we propose in this paper a new optimization of the serial nature of decoding the polar codes equivalent to binary linear block codes. In addition to the special nodes proposed by the simplified successive-cancellation list technique, we propose a new special node allowing to estimate in parallel the bits of its sub-code. The simulation is done in an additive white gaussian noise channel (AWGN) channel for several linear block codes, namely bose–chaudhuri–hocquenghem codes (BCH) codes, quadratic-residue (QR) codes, and linear block codes recently designed in the literature. The performance of the proposed technique offers the same performance in terms of frame error rate (FER) as the ordered statistics decoding (OSD) algorithm, which achieves that of maximum likelihood decoder (MLD), but with high memory requirements and computational complexity.&lt;/span&gt;

Polar-code-based information reconciliation scheme with the frozen-bit erasure strategy for quantum key distribution

Information reconciliation (IR) ensures the correctness of quantum key distribution systems, by correcting the error bits existed in the sifted keys. In this article, we propose a polar codes-based IR scheme with the frozen bits erasure strategy, where an equivalent transmission of sifted keys is conducted, so that the frozen bits in the decoding procedure is erased to 0. Thus, our IR scheme can be implemented efficiently without the assumption of true random numbers. Furthermore, we implement the proposed IR scheme with the fast simplified successive cancellation list decoder and its throughput reaches to 0.88Mbps with the yield of 0.8333, where the decoder list size is 16, the block size is 1Mb and the quantum bit error rate is 0.02.

Parity-Check-CRC Concatenated Polar Codes SSCFlip Decoder

Successive cancellation flip decoding requires a large number of extra successive cancellation decoding attempts at low signal-to-noise ratios (SNRs), resulting in high decoding complexity. In addition, it has a long decoding latency. Although modifications have been proposed in successive cancellation flip decoding, these still have high computational complexity at low SNRs due to a huge number of additional successive cancellation decoding attempts. It is desirable to detect the unsuccessful successive cancellation decoding process at an early stage in the additional successive cancellation flip attempts and stop it that can reduce the decoding complexity. This paper combines the parity-check-CRC concatenated polar codes with the low-latency simplified successive cancellation decoding and proposes a parity-check-CRC concatenated polar codes simplified successive cancellation flip (PC-CRC-SSCFlip) decoder. It further employs the parity-check vector to identify the unsuccessful simplified successive cancellation flip decoding at an early stage and terminates so that it can minimize the decoding complexity on average. Additionally, this work proposes an error-prone flipping list by incorporating the empirically observed indices based on channel-induced error distribution along with the first bit of each Rate-1 node. The proposed technique can identify more than one error-prone bit through a flipping list and correct them. In addition, the parity-check vector further narrows down the search space for the identification of erroneous decisions. Simulation results show that 60% of unsuccessful additional successive cancellation decoding attempts terminate early rather than decode the whole codeword. The proposed PC-CRC-SSCFlip decoder has approximately 0.7 dB and 0.3 dB gains over successive cancellation and successive cancellation flip decoders, respectively, at a fixed block error rate (BLER) = 10−3. Additionally, it reduces the average computational complexity and decoding latency of the successive cancellation flip decoder at low-to-medium SNRs while approaching successive cancellation decoding complexity at medium-to-high SNRs.

Decoding Reed-Muller Codes With Successive Codeword Permutations

A novel recursive list decoding (RLD) algorithm for Reed-Muller (RM) codes based on successive permutations (SP) of the codeword is presented. A low-complexity SP scheme applied to a subset of the symmetry group of RM codes is first proposed to carefully select a good codeword permutation on the fly. Then, the proposed SP technique is integrated into an improved RLD algorithm that initializes different decoding paths with random codeword permutations, which are sampled from the full symmetry group of RM codes. Finally, efficient latency and complexity reduction schemes are introduced that virtually preserve the error-correction performance of the proposed decoder. Simulation results demonstrate that at the target frame error rate of 10−3 for the RM code of length 256 with 163 information bits, the proposed decoder reduces 6% of the computational complexity and 22% of the decoding latency of the state-of-the-art semi-parallel simplified successive-cancellation decoder with fast Hadamard transform (SSC-FHT) that uses 96 permutations from the full symmetry group of RM codes, while relatively maintaining the error-correction performance and memory consumption of the semi-parallel permuted SSC-FHT decoder.

Improving Decodability of Polar Codes by Adding Noise

This paper presents an online perturbed and directed neural-evolutionary (Online-PDNE) decoding algorithm for polar codes, in which the perturbation noise and online directed neuro-evolutionary noise sequences are sequentially added to the received sequence for re-decoding if the standard polar decoding fails. The new decoding algorithm converts uncorrectable received sequences into error-correcting regions of their decoding space for correct decoding by adding specific noises. To reduce the decoding complexity and delay, the PDNE decoding algorithm and sole neural-evolutionary (SNE) decoding algorithm for polar codes are further proposed, which provide a considerable tradeoff between the decoding performance and complexity by acquiring the neural-evolutionary noise in an offline manner. Numerical results suggest that our proposed decoding algorithms outperform the other conventional decoding algorithms. At high signal-to-noise ratio (SNR) region, the Online-PDNE decoding algorithm improves bit error rate (BER) performance by more than four orders of magnitude compared with the conventional simplified successive cancellation (SSC) decoding algorithm. Furthermore, in the mid-high SNR region, the average normalized complexity of the proposed algorithm is almost the same as that of the SSC decoding algorithm, while preserving the decoding performance gain.

Parallelism Versus Latency in Simplified Successive-Cancellation Decoding of Polar Codes

This paper characterizes the latency of the simplified successive-cancellation (SSC) decoding scheme for polar codes under hardware resource constraints. In particular, when the number of processing elements P that can perform SSC decoding operations in parallel is limited, as is the case in practice, the latency of SSC decoding is O(N1-1/μ + N/P log2 log2 N/P), where N is the block length of the code and μ is the scaling exponent of the channel. Three direct consequences of this bound are presented. First, in a fully-parallel implementation where P = N/2, the latency of SSC decoding is O(N1-1/μ), which is sublinear in the block length. This recovers a result from our earlier work. Second, in a fully-serial implementation where P = 1, the latency of SSC decoding scales as O(N log2 log2 N). The multiplicative constant is also calculated: we show that the latency of SSC decoding when P = 1 is given by (2 + o(1))N log2 log2 N. Third, in a semi-parallel implementation, the smallest P that gives the same latency as that of the fully-parallel implementation is P = N1/μ. The tightness of our bound on SSC decoding latency and the applicability of the foregoing results is validated through extensive simulations.

High-throughput energy-efficient pipeline architecture for successive cancellation polar decoder

Polar codes are a class of block channel coding that can theoretically achieve channel capacity. The Polar codes are used in 5G applications due to superior error correction performance. Throughput and energy efficiency are important issues for efficient hardware implementation of Polar codes in real-world applications. This paper presents a high-throughput and energy-efficient pipeline architecture for a fast simplified successive cancellation decoding algorithm. In this architecture, the searching method in the Polar code data bit positions is improved which leads to ignoring computing all of the bits in the ordinary approach. This results in having efficient length for each node type which can make a tradeoff in latency and T/P. Furthermore, the supernode which helps to decrement the latency of the decoder are discussed and used to improve the decoder. Utilizing the supernodes, the number of pipeline stages decreases with a negligible corruption in the maximum frequency and throughput. The Polar decoder is implemented on Xilinx kintex-7 xc7k325t-2ffg900c. The achieved number of pipeline stages is 118 and the maximum clock frequency is 284 MHz on the target FPGA chip. The throughput of the decoder is up to 290.81 Gb/s and the latency is 415ns. The energy per bit is 3.14 pJ/bit. The implementing results confirm that the proposed decoder significantly improves the throughput and energy per bit in comparison with the related pipeline decoders.

Partial Order-Based Decoding of Rate-1 Nodes in Fast Simplified Successive-Cancellation List Decoders for Polar Codes

Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List (SCL) decoding supported by a Cyclic Redundancy Check (CRC) shows the best error-correction performance at the cost of a high decoding complexity. The decoding of Rate-1 nodes belongs to the most complex tasks in SCL decoding. In this paper, we present a new algorithm that largely reduces the number of considered candidates in a Rate-1 node and generate all required candidates in parallel. For this purpose, we use a partial order of the candidate paths to prove that only a specified number of candidates needs to be considered. Further complexity reductions are achieved by an extended threshold-based path exclusion scheme at the cost of negligible error-correction performance loss. We present detailed Application-Specific Integrated Circuit (ASIC) implementation data on a 28 nm Fully Depleted Silicon on Insulator (FD-SOI) Complementary Metal-Oxide-Semiconductor (CMOS) technology for decoders with code length 128. We show that the new decoders outperform state-of-the-art reference decoders. For list size 8, improvements of up to 158.8% and 62.5% in area and energy efficiency are observed, respectively.

Reduced-Complexity Successive-Cancellation Decoding for Polar Codes on Channels With Insertions and Deletions

In this paper, a simplified successive cancellation (SC) decoding algorithm for polar codes on insertion/deletion error channels is proposed. First, the SC decoding is designed to decode polar codes on insertion/deletion channels and the joint weight distribution is derived to measure the occurrence probability of different scenarios. Some scenarios with small occurrence probability can be pruned to obtain lower decoding complexity with negligible performance loss. Inspired by this, a fixed pruning strategy (FPS) is proposed to reduce the decoding complexity, which can prune as many scenarios as possible with the given performance requirement. By exploiting the periodicity of the joint weight distribution, the upper bound of the block error rate of the pruned SC decoding is derived. Furthermore, according to the convergence of the upper bound, a dynamic self-adjusting pruning strategy is designed to further reduce the decoding complexity and improve the flexibility of the pruning algorithm. Simulation results show that the decoding complexity of the proposed pruning-based decoding algorithms is significantly reduced compared to the state-of-the-art scenario simplified SC decoding algorithm.

SIMPLIFIED SUCCESSIVE-CANCELLATION LIST POLAR DECODING FOR BINARY LINEAR BLOCK CODES

This paper aims to take advantage of the performances of polar decoding techniques for the benefit of binary linear block codes (BLBCs) with the main objective is to study the performances of the SSCL decoding for short-length BLBCs. Polar codes are one of the most recent error-correcting codes to be invented, and they have been mathematically demonstrated to be able to correct all errors under a specific situation, using the successive-cancellation decoder. However, their performances for real-time wireless communications at short block lengths remain less attractive. To take advantage of the performance of these codes in favor of error correction codes of short block length, an adaptation of the simplified successive-cancellation list as a decoder for polar codes for the benefit of short block length binary linear block codes is presented in this paper. This adaptation makes it possible to take advantage of the performances of less complex decoding methods for polar codes for BLBCs with latency and complexity optimization of the standard successive-cancellation list decoder. The experiment shows that the method can achieve the performances of the most famous order statistic decoder for binary linear block codes, which can achieve the performances of maximum-likelihood decoding with computational complexity and memory constraints.

A correlation-breaking interleaving of polar codes in concatenated systems

It is known that the bit errors of polar codes with successive cancellation (SC) decoding are coupled. However, existing concatenation schemes of polar codes with other error correction codes rarely take this coupling effect into consideration. To achieve a better error performance of concatenated systems with polar codes as inner codes, one can divide all bits in an outer block into different polar blocks to completely de-correlate the possible coupled errors in the transmitter side. We call this interleaving a blind interleaving (BI) which serves as a benchmark. Two BI schemes, termed BI-DP and BI-CDP, are proposed in the paper. To better balance performance, memory size, and the decoding delay from the de-interleaving, a novel interleaving scheme, named the correlation-breaking interleaving (CBI), is proposed. The CBI breaks the correlated information bits based on the error correlation pattern proposed and proven in this paper. The proposed CBI scheme is general in the sense that any error correction code can serve as the outer code. In this paper, Low-Density Parity-Check (LDPC) codes and BCH codes are used as two examples of the outer codes of the interleaving scheme. The CBI scheme 1) can keep the simple SC polar decoding while achieving a better error performance than the state-of-the-art (SOA) direct concatenation of polar codes with LDPC codes and BCH codes; 2) achieves a comparable error performance as the BI-DP scheme with a smaller memory size and a shorter decoding delay. Numerical results are provided to verify the performance of the BI schemes and the CBI scheme.

Minimum-Combinations Set-Based Rate-1 Decoder for Fast List Decoding of Polar Codes

Fast Simplified Successive-Cancellation List (Fast-SSCL) decoding has significantly reduced the decoding latency of polar codes by implementing fast parallel operations in local decoders. This letter presents a Minimum-Combinations (MC) set <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathcal {C} $ </tex-math></inline-formula> to speed up the splitting process of Rate-1 decoder for fast list decoding of polar codes. The proposed set, eliminating the flipping bit indices combinations with less reliability, is collected in advance and only relative to the size of the list. The experiments demonstrate that compared with existing Fast-SSCL decoding, our proposed method achieves significant latency reduction while preserving the bit and frame error rate.

Error correction in data storage systems using polar codes

This paper investigates error correction in two-dimensional (2-D) intersymbol interference (ISI) channels using polar codes. 2-D channels offer high data storage capacity compared to traditional one-dimensional (1-D) channels but suffer from greater ISI effects. Error correction codes can be used to mitigate the effects of ISI in 2-D data storage systems and improve their performance and reliability. Polar codes achieve the symmetric capacity for the class of binary-input discrete memoryless channels (B-DMCs). A post-processing technique is proposed to improve the performance of polar codes in the 2-D ISI channel. The simplified successive cancellation (SSC) polar decoder is useful for data storage systems owing to its good waterfall region performance, low error floors and good throughput rates and is therefore adopted for the study. Simulation results indicate that the proposed technique has an error correction performance comparable to some existing decoders and has better performance than other decoding techniques.

Sublinear Latency for Simplified Successive Cancellation Decoding of Polar Codes

This work analyzes the latency of the simplified successive cancellation (SSC) decoding scheme for polar codes proposed by Alamdar-Yazdi and Kschischang. It is shown that, unlike conventional successive cancellation decoding, where latency is linear in the block length, the latency of SSC decoding is sublinear. More specifically, the latency of SSC decoding is O(N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-1/μ</sup> ), where N is the block length and μ is the scaling exponent of the channel, which captures the speed of convergence of the rate to capacity. Numerical results demonstrate the tightness of the bound and show that most of the latency reduction arises from the parallel decoding of subcodes of rate 0 or 1.

Simplified Successive Cancellation 알고리즘을 지원하는 효율적인 Polar 디코더의 설계 및 구현

Simplified Successive Cancellation 알고리즘을 지원하는 효율적인 Polar 디코더의 설계 및 구현