Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing

Abstract

Benefiting for its capacity-achieving property, the polar codes have attracted wide attention in various forward error correction (FEC) codes. Although Successive-Cancellation (SC) decoders have low hardware complexity, their limited thoughput leads to low hardware efficiency. In this paper, two novel processing elements (PE) units for SC decoders are proposed by the reconstruction of key functions. Approximate comparator and adder-subtractor are developed in the proposed PEs to further enhance the hardware efficiency of the SC decoders with neglectable bit error rate (BER) performance degradation. The designs are implemented and evaluated on 28nm CMOS technology. Simulation results indicate that the area efficiency of two designs are 17.758r <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {Gb/s/mm^{2}}$ </tex-math></inline-formula> and 14.416r <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {Gb/s/mm^{2}}$ </tex-math></inline-formula> with 1024-bit code length and the code rate r, which are 26.7% and 9.7% better than the state-of-the-art SC implementations. Moreover, the low complexity Fast Simplified SC (Fast-SSC) decoder implemented with proposed approximate PEs has 60.3% area efficiency improvement than the prior Fast-SSC decoders with equivalent BER performance.