Simple Circuit Technique Research Articles

A detailed study of the current‐reuse VCO's operation and a simple circuit technique to generate intrinsic‐balanced outputs

SummaryIn the first part of this paper, we closely examine well‐known methods for balancing the output power level of the pseudo‐differential current‐reuse voltage‐controlled oscillator. We scrutinize their effectiveness in terms of canceling output mismatches, insensitivity to process, voltage, and temperature variations, and their capability of not degrading phase noise performance. Through analyses and simulations, it is shown that contrary to common belief, some techniques are not as effective as previously thought and should be employed only under specific circumstances. The best conventional approach is proven to be the use of a common‐mode shunting capacitor at the inductor's center tap node to create a virtual ground. In the second part, it is demonstrated that the current‐reuse voltage‐controlled oscillator can intrinsically produce balanced outputs without using any additional techniques or extra passive or active components. Using single‐ended tank capacitors instead of differential ones, the common‐mode voltage of the outputs is shunted to the real ground. This technique reintroduces a reference voltage to the tank circuit, forcing the oscillator to achieve equilibrium between positive and negative swings. The proposed current‐reuse oscillator is designed and post‐layout simulated in a 65‐nm CMOS process, covering a frequency range of 4.84–6.38 GHz with an average power consumption of 0.65 mW. It produces balanced outputs with an amplitude error of less than ±0.2% and achieves a phase noise of −126.7 dBc/Hz and FoMT of 201.8 dB at a 3‐MHz offset frequency.

A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers

This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden's and Schreier's figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs.

Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.

A simple circuit technique to relax the feedback timing of ΔΣ ADC for high-speed and high-accuracy applications

A novel and simple circuit technique to relax the feedback timing of input feed-forward ΔΣ analog-to-digital converter (ADC) is proposed for wideband and high-accuracy applications. The proposed method allows the use of low-speed comparator and DEM logic even for high-speed operation which helps to reduce the power consumption. A delta-sigma ADC with relaxed feedback timing was designed and simulated. The results verify the advantages of the proposed technique.

Novel inspection-based mid-band derivations for CMOS cascodes and g m-boosted topologies along-with simplified compound structure gain-analysis

This article demonstrates simplified mid-band derivations for CMOS cascode and gm-boosted cascode. While the cascode mid-band analysis is addressed in some textbooks through varying brief treatments, it is provided in this paper in a more in-depth and consolidated form using an easy approach. The detailed analysis of gm-boosted cascode stage is mostly not available in textbooks (or any Web source) despite being an important analog building block in achieving gain enhancements. The mid-band analysis of this stage is made easy in this paper using a simple short circuit and inspection technique. There is no need to write or solve lengthy equations. Transformation of dependent current sources through "opportunistic short circuits" is utilized often in achieving this ease in derivation. An interesting new concept of "Algebraic ground" or "Meta-ground" is introduced in relation to the gm-boosted cascode. Some novel compound cascode stages with simplified approach to their mid-band derivations is also provided. Additional insight is also provided through a comparison of the cascode with the gm-boosted cascode using the simplified models and derivations which is rarely available elsewhere.

A Wide-Range On-Chip Leakage Sensor Using a Current–Frequency Converting Technique in 65-nm Technology Node

As technology moves toward the submicrometer regime, leakage current due to aggressive scaling and parameter variation has become a major problem in high-performance integrated circuit designs. Therefore, accurate measurement of the leakage current flowing through transistors has become a critical task for better understanding of process and design. In this brief, we propose a simple on-chip circuit technique for measuring a wide-range static standby (or leakage) current in a 65-nm technology with high accuracy. The circuit consists of a current amplifier, a bias stabilizer, and a voltage-controlled oscillator. The proposed leakage sensor is designed to measure leakage currents from 20 pA to 20 nA. Simulation results show that the proposed sensor has less than 8.4% error over a wide range of leakage currents (i.e., three orders of magnitude). Chip measurement results also indicate that the proposed leakage sensor is operating properly and measures the standby leakage current values of the devices under test within the possible range at different temperatures. The power consumption of the proposed leakage sensor was 0.6 mW when the leakage current was 1 nA, and the active area was 0.007 mm 2.

On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems

Leading-edge VLSI systems, essentially multiprocessor systems-on-chip, have a wide range of components integrated together and operating in unison. They can be analyzed as flow networks in which the system performance depends on the bandwidth, transmission time, and queueing delay characteristics of the individual components, their connectivity and interactions, as well as the traffic patterns they encounter. The flow in various parts of the system must ideally be distributed so as to extract the maximum throughput possible with minimum end-to-end delays. Such an ideal distribution for flow networks has previously been obtained using simple electrical circuits. We demonstrate a similar methodology for typical VLSI systems and provide the necessary extensions of the theory. We empirically validate the methodology using a cycle-accurate simulation model as the reference. We find this methodology to supply better distributions in the average case and comparable distributions in the worst case as compared to standard search procedures such as random sampling and simulated annealing. The real strength is that it provides a speedup of several orders of magnitude, i.e., 3-5 orders in our experiments. Thus it is an elegant means for analyzing and optimizing the flow in VLSI systems, which can easily be incorporated into design procedures, compilers and on-chip modules for real-time allocations.

PSRR improvement technique for single supply class AB power amplifiers

A simple circuit technique for improving the midband positive power supply rejection ratio (PSRR dd ) of gain boosted class AB power amplifiers is presented. The technique takes advantage of the bias network and inherent narrow gain boosting amplifier bandwidth and therefore does not require any additional components. Measurements show that more than 20 dB improvement in the midband PSRR dd is obtainable at a frequency of 100 kHz

PVT-Aware Leakage Reduction for On-Die Caches With Improved Read Stability

Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-/spl mu/m 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%.

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-/spl Omega/ input and output matching is demonstrated in 0.18-/spl mu/m CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm/sup 2/.

A simple wide-band CMOS based true rms-to-dc converter

A simple integrable circuit technique for the realization of a wide bandwidth current-mode CMOS true rms-to-dc converter is proposed. The realization scheme is based on the implicit computation method that makes use of the characteristic of a CMOS squaring circuit, where the transistors are biased in their saturation regions. The conversion circuit consumes very low power due to the bias current of the circuit provided by the root-mean-square current I RMS. The performance of the proposed circuit is studied through PSPICE simulation and experimental results.

Microwave I-Q vector modulator using a simple technique for compensation of FET parasitics

The analysis and design of an improved technique for the realization of vector modulators using analog reflection-type circuits are presented. The analysis focuses on the detrimental effect that the parasitic elements of the FET variable-resistance elements have on the 360/spl deg/ phase and amplitude control. It is shown that a simple circuit technique can be used to compensate for the parasitic effects and achieve a near-ideal constellation. Compared with the balanced structure, the proposed technique leads to a much smaller circuit area and does not require additional complementary control signals. This makes it better suited to commercial wireless applications where low cost is paramount. Simulation and experimental results for an L-band prototype are presented.

PULSED LOW POWER CMOS

A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.

Using cache mechanisms to exploit nonrefreshing DRAMs for on-chip memories

On-chip memories are becoming an established feature in single-chip microprocessor designs because they significantly improve performance. It is particularly important for single-chip reduced instruction set computer (RISC) microprocessors to include large, high-speed memories, because RISC chips must reduce off-chip memory delays to achieve the shortest possible cycle time. The use of dynamic RAM for all on-chip cache results in all important increased density of local memory for a given scarce chip area, but complicates the processor control due to the inherent requirement for refreshing. By using simple circuit techniques and making a few modifications to cache organization, the refreshing requirement of dynamic RAM can be eliminated. This new cache design approach is described. It makes use of a selective invalidation technique that invalidates only those cache entries that are not fresh. This is accomplished without interrupting the processor execution stream and without degrading the cache performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Programmable current-mode neural network for implementation in analogue MOS VLSI

This paper presents simple and efficient circuit techniques for the implementation of feedback and feedforward neural networks in analogue MOS VLSI. Synaptic weight storage is achieved using programmable threshold-voltage devices, such as the metal-nitride-semiconductor (MNOS) transistor and the floating-gate MOS (FGMOS) transistor. Basic electronic neural functions, such as adaptive weighted summation and sigmoidal nonlinearity functions, are implemented using simple current-mode analogue signal processing building blocks. This is particularly attractive when neural networks of increased complexity are implemented in modern scaled VLSI technologies, where voltage signal handling is severely limited for analogue applications. A four-neuron chip is designed, using the new current-mode building blocks, fabricated and experimentally verified using the MOSIS 2μm double-poly, double-metal p-well CMOS process. Intensive computer simulation and experimental results are provided.

A versatile CMOS linear transconductor/square-law function

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

Testability enhancement of domino CMOS logic

A simple circuit technique to enhance the testability of domino CMOS circuits is presented. The fact that domino CMOS gates always have their outputs precharged low enables one to test for output stuck-at-one faults by a simple modification of the domino gate.

Two-domain analysis of field-producing bodies, using fictitious poles

An unconventional numerical method is presented for analysing the behaviour of a field-producing body, e.g. a bar magnet. The body shape is restricted to axisymmetry and to mirror-image symmetry about a central plane, but is otherwise general. The body internal features are likewise general, and may include mixed materials having non-linear properties. The basic principle is always to have a specified surface potential distribution upon trial. It is shown that the external and internal analyses may then proceed independently. Externally, Laplace's equation is solved using a sparse set of fictitious internal poles. The solution is self-validating, and provides a direct transformation from surface potential to internal body flux distribution taking account of any applied external field. Internally, flux is then converted using simple circuit technique to a new surface potential distribution.

Wide-Band Varactor-tuned Coaxial Oscillators

An experimental investigation into the effects of package and circuit reactances on wide-band varactor-tuned oscillators is described. The results are used to design an X-band Gunn coaxial oscillator with a tuning range in excess of 3 GHz. It is shown that the stray reactance, junction capacitance, and bond-wire inductance affect the varactor tuning characteristics. The characteristics are conveniently displayed by the reflection phase variation with tuning voltage and frequency. A general theory for wide-band varactor-tuned oscillators is presented which is related to the impedance characteristics. These results are used to design three coaxial varactor-tuned oscillators. The first two oscillators are series arrangements while the third oscillator is a parallel arrangement. A simple circuit technique is used to improve the tuning range of each arrangement. This technique is shown to increase the coupling to the varactor diode and decrease the oscillator Q by reactance compensation.

Frequency-stable pulsed Gunn oscillators

Pulsed Gunn-diode oscillators with low frequency drift across the pulse (chrip) have been produced in the X and J bands. Using simple circuit techniques, uncompensated chirps from 30 to 100 MHz are reduced to less than 2 MHz.