Abstract

SummaryIn the first part of this paper, we closely examine well‐known methods for balancing the output power level of the pseudo‐differential current‐reuse voltage‐controlled oscillator. We scrutinize their effectiveness in terms of canceling output mismatches, insensitivity to process, voltage, and temperature variations, and their capability of not degrading phase noise performance. Through analyses and simulations, it is shown that contrary to common belief, some techniques are not as effective as previously thought and should be employed only under specific circumstances. The best conventional approach is proven to be the use of a common‐mode shunting capacitor at the inductor's center tap node to create a virtual ground. In the second part, it is demonstrated that the current‐reuse voltage‐controlled oscillator can intrinsically produce balanced outputs without using any additional techniques or extra passive or active components. Using single‐ended tank capacitors instead of differential ones, the common‐mode voltage of the outputs is shunted to the real ground. This technique reintroduces a reference voltage to the tank circuit, forcing the oscillator to achieve equilibrium between positive and negative swings. The proposed current‐reuse oscillator is designed and post‐layout simulated in a 65‐nm CMOS process, covering a frequency range of 4.84–6.38 GHz with an average power consumption of 0.65 mW. It produces balanced outputs with an amplitude error of less than ±0.2% and achieves a phase noise of −126.7 dBc/Hz and FoMT of 201.8 dB at a 3‐MHz offset frequency.

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