SIMD Processor Array Research Articles

A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network

A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the von Neumann bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.

Mixed signal SIMD processor array vision chip for real-time image processing

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.

A high speed programmable focal-plane SIMD vision chip

A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

AbstractA high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A "Equation missing" pixel proof-of-concept chip was fabricated in a 0.35 "Equation missing"m standard CMOS process, with a pixel size of 35 "Equation missing"m "Equation missing" 35 "Equation missing"m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.

General-purpose 128×128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.

A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging

This paper presents a multiresolution general-purpose high-speed machine vision sensor with on-chip image processing capabilities. The sensor comprises an innovative multiresolution sensing area, 1536 A/D converters, and a SIMD array of 1536 bit-serial processors with corresponding memory. The sensing area consists of an area part with 1536 /spl times/ 512 pixels, and a line-scan part with a set of rows with 3072 pixels each. The SIMD processor array can deliver more than 100 GOPS sustained and the on-chip pixel-analysing rate can be as high as 4Gpixels/s. The sensor is ideal for high-speed multisense imaging where, e.g., color, greyscale, internal material light scatter, and 3-D profiles are captured simultaneously. When running only 3-D laser triangulation, a data rate of more than 20 000 profiles/s can be achieved when delivering 1536 range values per profile with 8 bits of range resolution. Experimental results showing very good image characteristics and a good digital to analog noise isolation are presented.

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.

Parallel Strategies for Rank-k Updating of the QR Decomposition

Parallel strategies based on Givens rotations are proposed for updating the QR decomposition of an n × n matrix after a rank-k change (k < n). The complexity analyses of the Givens algorithms are based on the total number of Givens rotations applied to a 2-element vector. The algorithms, which are extensions of the rank-1 updating method, achieve the updating using approximately 2(k + n) compound disjoint Givens rotations (CDGRs) with elements annihilated by rotations in adjacent planes. Block generalization of the serial rank-1 algorithms are also presented. The algorithms are rich in level 3 BLAS operations, making them suitable for implementation on large scale parallel systems. The performance of some of the algorithms on a 2-D SIMD (single instruction stream--multiple instruction stream) array processor is discussed.

Ordinary linear model estimation on a massively parallel SIMD computer

Efficient algorithms for estimating the coefficient parameters of the ordinary linear model on a massively parallel SIMD computer are presented. The numerical stability of the algorithms is ensured by using orthogonal transformations in the form of Householder reflections and Givens plane rotations to compute the complete orthogonal decomposition of the coefficient matrix. Algorithms for reconstructing the orthogonal matrices involved in the decompositions are also designed, implemented and analyzed. The implementation of all algorithms on the targeted SIMD array processor is considered in detail. Timing models for predicting the execution time of the implementations are derived using regression modelling methods. The timing models also provide an insight into how the algorithms interact with the parallel computer. The predetermined factors used in the regression fits are derived from the number of memory layers involved in the factorization process of the matrices. Experimental results show the high accuracy and predictive power of the timing models. Copyright © 1999 John Wiley & Sons, Ltd.

High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications

Edited by: Rajkumar Buyya Prentice Hall PTR, Upper Saddle River, NJ, 1999 Volume 1: 881pp, ISBN 0-13-013784-7, $54.00 Volume 2: 700pp, ISBN 0-13-013786-5, $54.00 I used the two books as part of a course that I taught at IIT Delhi during July-Dec 1999. The course was called Special Topics in Computers and included Masters students from the Departments of Electrical Engineering and Computer Science. The idea behind the course was to introduce elements of Distributed and Clustered Computing to students who already have some background in Computer Architecture. In my opinion, a single course in Computer Architecture at the Masters level cannot do justice to the developments that have taken place in this exciting field over the past decades. I have been teaching Computer Architecture at IIT Delhi for about 8 years now and find that the number of topics that I have to include in the course has been increasing very quickly over the years! In 1992, when I first taught the course, I used to teach about Pipelined Computers, Systolic Arrays, SIMD array processors, and Multiprocessors. As time has passed, it has become necessary to include topics such as high-performance interconnection networks, wormhole routing, cache coherence protocols, instruction pipelines, superscalar processors, and instruction-level parallelism. More recently, I have realized that it is also necessary to teach elements of distributed computing and clustered computing. I believe that a course on selected topics from distributed and clustered computing is essential to all branches of Engineering today. High-performance computing is essential to all branches of Engineering, and high-performance clustered computing on clusters of workstations/PCs makes a lot of economical sense. A course such as this is interesting because it is easy for the students to practice what is taught in such a class without too many infrastructures. This makes the course very exciting to students. When I taught parallel algorithms in my class, I could not ask my students to develop these algorithms for lack of good infrastructure. However, a cluster of workstations and PCs is available in almost every University today. Distributed computing is highly popular with students. Students are eager to learn Java and network programming. Rajkumar Buyya's edited volumes have arrived at the right time to provide the right kind of teaching material for the type of course, which I have above mentioned. The first volume covers architectural and system-level issues of clustered computing systems. It has 36 chapters organized into four sections, spanning 811 pages. Section I develops the motivation for high-performance clustered computing. Section II introduces various networking protocols and I/O mechanisms that are useful in clustered computing. Section III covers OS issues such as process scheduling and load balancing. Section IV includes a number of case studies of existing systems. The editor has made a considerable effort in gathering learning material for the volume. I think that this volume could be an excellent text for an advanced course on Computer Architecture. In the course that I taught, I used parts of Section I and IV. To me, the second volume proved more useful. The second volume concerns with applications of clustered computing and applications programming. It is divided into 3 sections. There are 29 chapters that span 604 pages. Both volumes have carefully prepared Glossaries and Indexes. The first section of the second volume is on various programming environments and development tools. Although I limited myself to the discussion of the Parallel Virtual Machine (PVM) and Message Passing Interface (MPI), the editor has also included entire chapters on linking of these two environments, active objects, component-based approach, LiPS, and WebOS. There is a chapter of debugging parallelized code that can be highly valuable for students and developers of applications. The second section is on Java for high-performance computing. These topics raised a lot of interest among students when I taught the course. The third section is on specific algorithms and applications such as parallel genetic algorithms, parallel simulation, distributed database systems, graphics and image processing. The authors who have contributed to the two volumes are all known experts in the areas of Computer Architecture, Computer Networks, Distributed Computing, and Operating Systems. The authors and the editor must be congratulated on this extraordinary effort to compile so much useful material under one place. The books can not only serve as reference material to professional programmers in the modern IT industry, it can also serve as excellent teaching material for courses related to Computer Architecture, Distributed Computing, and Operating Systems. The web page that the editor has created for the book is also a wonderful repository of learning material available on the web. I recommend these volumes wholeheartedly to all serious researchers and students interested in the areas of high-performance computing in general and clustered computing in particular. C. P. Ravikumar, IIT Delhi

Motion Analysis on the Micro Grained Array Processor

Motion analysis plays a key role in video coding (e.g., video telephone, MPEG, HDTV) and computer vision systems (e.g., image segmentation, structure from motion). Motion estimation methods can be classified into three groups – matching-based, gradient-based, and frequency-based methods. The block matching algorithm (BMA) has been widely used for region matching in image coding, for example in MPEG (Motion Picture Expert's Group). Optical flow computation based on the spatio-temporal constraint equation has been broadly used in image segmentation to compute each pixel's velocity on a moving object. For both of these tasks, dedicated ASIC systems have been developed and widely used. Unfortunately, such systems have the disadvantage of restricted adaptability. The Micro Grained Array Processor (MGAP), which is a fine-grained, mesh-connected, SIMD array processor being developed at Penn State University, can provide a more regular, flexible, and efficient approach for solving, in real time, these two important computations.In this paper, we propose a new data flow scheme for an efficient, systolic, full-search BMA on programmable array processors so that we can process as many adjacent template blocks as possible in unison in order to reduce the data memory accesses. In particular we present an efficient implementation of the BMA on the MGAP. As a result, the BMA for the MPEG SIF video format (352 × 240 pixels) with a block size of 16 × 16 pixels, a displacement range of 16 pixels, and frame rate of 30 frames/sec can be computed at real-time processing rates on the MGAP. We also show a real-time mapping to the MGAP of the optical flow computation for images of size 256 × 256 pixels.

Data-parallel C on a reconfigurable logic array

The existence of reconfigurable logic arrays has made it possible to create on the same physical hardware platform many different virtual circuits: A configuration bit stream loaded into the logic array determines the virtual circuit that is to be emulated. The virtual logic can be used to create new instructions that supplement the instruction set of a conventional processor (as demonstrated, for example, in (Athanas and Silverman, 1993) and (Agarwal et al., 1994)) or alternatively can operate as a parallel coprocessor, as shown in the Splash systems (Gokhale et al., 1991) and (Gokhale and Minnich, 1993). The ease of hardware reconfiguration has not been accompanied by a corresponding capability in the software environment. In most cases, schematic capture tools, textual hardware description languages, or low-level vendor-specific tools must be used to create new configurations. Research into high-level synthesis for reconfigurable arrays has begun, however, as evidenced by the PRISM-2 tools of (Agarwal et al., 1994) and the dbC translation system of (Gokhale and Minnich, 1993). The ability to write algorithms for these arrays in a high-level procedural language is key to their effective use. In this paper we describe the data-parallel bit C system that is used to program a reconfigurable logic array as a custom SIMD coprocessor. The dbC language has bit-oriented extensions to C, which give the programmer control over the size of parallel data objects so that the data size requirements of the algorithm can be accurately reflected in the hardware. The data parallel extensions provide the ability to define a SIMD processor array; to operate on data in the processors' memories; to perform global reductions over the processor array; and to communicate data between nearest-neighbor processing elements. We describe the major components of our translation system and show how it is mapped onto the Splash 2 system.

A monolithic processing subsystem

A single-chip 120 MFLOP (peak) 26 million transistor digital processing subsystem with 512 kilobytes of on-chip SRAM has been developed. This general purpose 32-bit floating point Harvard architecture device, which incorporates sophisticated communication capabilities and at maximum throughput dissipates less than 2 W, can be used as a stand-alone processor or as a building block for both SIMD and MIMD processor arrays. This paper describes physical and functional features of the chip, and provides some discussion of how it can be applied. >

Linear generalized Hough transform and its parallelization

Abstract The Generalized Hough Transform (GHT) proposed by Ballard 1 is an effective method for recognizing objects of arbitrary shape. It converts a problem of global pattern matching into local peak searching. However, the GHT has difficulty in handling occluded objects. It also suffers from the congestion at the single peak point when attempting its potential parallelization. In this paper, we present a Linear Generalized Hough Transform (LIGHT) in which a linear numeric pattern is used to replace the single peak in the GHT. The LIGHT is more capable of detecting partially occluded objects. Moreover, it is well-suited for parallelization, especially on SIMD array processors. Several sequential and parallel LIGHT algorithms and our preliminary results are presented. The impact of noise on the effectiveness of the LIGHT algorithm is studied. The result for parallel implementation is obtained from an SIMD onedimensional array processor (the AIS-4000 Vision Processor with 512 processing elements). A speed-up factor of two orders of magnitude is achieved.

IMAP: INTEGRATED MEMORY ARRAY PROCESSOR

This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this paper describes orthogonal IMAP, which has an extended IMAP architecture. The basic IMAP uses a conventional memory cell, while the orthogonal IMAP uses an orthogonal memory for holding images.

Stochastic Ray Tracing Using SIMD Processor Arrays

Stochastic ray tracing is one of the most elegant methods for anti-aliasing and for generating such phenomena as soft shadows, fuzzy reflections, depth of field, and motion blur, which are difficult to accomplish with the conventional ray-tracing algorithm. Unfortunately, it makes use of stochastic sampling, which requires more than one sample for each pixel. One possible way to speed up ray tracing is to explore the inherent parallelism of the algorithm. In the past few years, the major focus of parallel ray-tracing research has been on the use of MIMD architectures. Although SIMD architectures may be ideal for ray tracing simple scenes, they have been thought unsuitable for ray tracing complex scenes. However, by using scene coherence, we have found that stochastic ray tracing using SIMD processor arrays can be as efficient as most of the existing MIMD ray-tracing algorithms and more cost effective.

Efficient parallelism using indirect addressing in SIMD processor arrays

We investigate the use of indirect addressing in processor arrays as a way to improve the processing of recursive neighbourhood (i.e., data-dependent) operations. The efficiency and speed for processing six such operations is measured for both window and crinkle mapping, and evaluated against the efficiency of traditional updating methods.

A four-processor building block for SIMD processor arrays

A four-processor chip, for use in processor arrays for image computations, is described. The large degree of data parallelism available in image computations allows dense array implementations where all processors operate under the control of a single instruction stream. An instruction decoder shared by the four processors on the chip minimizes the pin count allocated for global control of the processors. The chip incorporates an interface to an external SRAM (static RAM) for memory expansion without glue chips. The full-custom 2- mu m CMOS chip contains 56669 transistors and runs instructions at 10 MHz. Five hundred and twelve 16-b processors and 4 Mbyte of distributed external memory fit on two industry standard cards to yield 5-billion instructions per second peak throughout. As image I/O can overlap perfectly with pixel computation, an array containing 128 of these chips can provide more than 600 16-b operations per pixel on 512*512 images at 30 Hz. >

Parallel algorithms for SIMD computers

Parallel Algorithms that manipulate multi-dimensional arrays on two-dimensional SIMD processor arrays are described here. The definition of these algorithms, which will be called COMPRESS and EXPAND is taken from APL and FORTRAN 8X. These algorithms have already been studied under the constraint that the number of elements is equal to the number processing elements. In the algorithms presented here these restrictions are lifted. Therefore the application of these algorithms contributes to transforming array languages into more general use languages.