Data-parallel C on a reconfigurable logic array

Abstract

The existence of reconfigurable logic arrays has made it possible to create on the same physical hardware platform many different virtual circuits: A configuration bit stream loaded into the logic array determines the virtual circuit that is to be emulated. The virtual logic can be used to create new instructions that supplement the instruction set of a conventional processor (as demonstrated, for example, in (Athanas and Silverman, 1993) and (Agarwal et al., 1994)) or alternatively can operate as a parallel coprocessor, as shown in the Splash systems (Gokhale et al., 1991) and (Gokhale and Minnich, 1993). The ease of hardware reconfiguration has not been accompanied by a corresponding capability in the software environment. In most cases, schematic capture tools, textual hardware description languages, or low-level vendor-specific tools must be used to create new configurations. Research into high-level synthesis for reconfigurable arrays has begun, however, as evidenced by the PRISM-2 tools of (Agarwal et al., 1994) and the dbC translation system of (Gokhale and Minnich, 1993). The ability to write algorithms for these arrays in a high-level procedural language is key to their effective use. In this paper we describe the data-parallel bit C system that is used to program a reconfigurable logic array as a custom SIMD coprocessor. The dbC language has bit-oriented extensions to C, which give the programmer control over the size of parallel data objects so that the data size requirements of the algorithm can be accurately reflected in the hardware. The data parallel extensions provide the ability to define a SIMD processor array; to operate on data in the processors' memories; to perform global reductions over the processor array; and to communicate data between nearest-neighbor processing elements. We describe the major components of our translation system and show how it is mapped onto the Splash 2 system.