Silvaco TCAD Research Articles

Reduced Graphene-Oxide-Based Silk-FET: A Facile Platform for Low Power and Room Temperature Detection of Formaldehyde

This article demonstrates the potential of silk film as gate dielectric in FET-based gas sensor. L-ascorbic acid (LAA) reduced graphene oxide (rGO) was used as semiconducting channel which acts as the sensing layer of the FET-based sensor. The morphology and capacitance of silk film were investigated to introspect two seldomly explored quantities: porosity and dielectric constant. The measured dielectric constant of silk film lies in the range of 32–13 in the low-frequency regime (40–100 Hz). Silk film also exhibited uniform, nonporous, smooth morphology. The Silk-FET device exhibited selective response toward formaldehyde (HCHO) among seven volatile organic compounds (VOCs), and rGO ensured room temperature sensing. During the adsorption of formaldehyde, electrons’ transfer takes place from formaldehyde to rGO, reducing the hole concentration of the channel. This leads to reduction in output current, revealing p-type characteristics of the device. The transfer and output characteristics also exhibited similar p-type nature. Device’s threshold voltage shift is also prominent with the exposure to formaldehyde. The gate bias played a pivotal role in improving the device performance. At 1.15-V gate voltage, the response was enhanced by 2.8 times for 45-ppm formaldehyde. The device exhibited maximum response at a gate voltage of 1.15 V, ensuring low-power operation of the FET device. The device’s response and recovery time were calculated as 97 and 280 s, respectively, at 180-ppm formaldehyde. The sensing behavior of the system was also reaffirmed through the TCAD SILVACO simulations. The energy band diagram revealed the depletion of carriers at rGO with adsorption of formaldehyde.

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

Performance of MOS Capacitor with Different Dielectric Material Simulated Using Silvaco TCAD Tools

Metal oxide semiconductor (MOS) capacitor is a trilayer device that comprises of metal, dielectric, and semiconductor layer. The advancement of MOS technology has greatly give huge improvement to MOS devices which lead to scaling down the MOS devices. The reduction of dielectric thickness of conventional dielectric material has coming to an end, therefore as alternative new material with high mobility carrier is suggested to overcome the problem. The objectives of this work are to study the performance of MOS capacitor. Two parameters were varied, first the semiconductor material which is silicon (Si), germanium (Ge) and silicon germanium (SiGe) and second is the dielectric material that is silicon dioxide (SiO2) and silicon nitride (Si3N4). The performance of the MOS capacitor is evaluated based on the capacitance-voltage (C-V) and current-voltage (I-V) characteristics. Silvaco TCAD tool were use as as simulation tool for the method of investigation. Result shown that the performance of the MOS capacitor increased when Ge and SiGe were used as semiconductor material and Si3N4 as dielectric layer. It can see that with VT of 4.15 V for MOS with Ge and 4.28 V for MOS with SiGe. For the C-V properties Cmax value for both devices are F and F, respectively. The results show that there is around 100% increment in capacitance value when Ge is used as semiconductor layer but there is no increment or decrement in capacitance value when SiGe is used. Based on the obtained results, Ge is chosen as the best semiconductor material.

Study of Porous III-V Surface Structure via Etching Process: Effect of Pore Depth

In this project, the surface structure of III-V semiconductor, GaAs, was altered to enhance the optical and electronic properties of the semiconductor. This project involved the designing and fabrication of non-porous and porous GaAs structures using SILVACO TCAD tools. The porous GaAs with different pore depth were designed and simulated to investigate the effect of pore depth on the optical and electrical properties of GaAs semiconductor. The pore depth of porous GaAs structure was varied with 2, 4, 6 and 8 μm. The porous GaAs structures were then tested for the metal-semiconductor-metal (MSM) photodetector device application. The non-porous and porous GaAs MSM photodetectors were compared systematically through current-voltage (I-V) characteristics, current gain, and spectral response. The result showed that the porous GaAs MSM photodetector has better performance in terms of electrical and optical properties than the non-porous photodetector. Amongst the MSM GaAs photodetectors, the porous GaAs photodetector with pore depth of 6 μm obtained the highest current gain value of 3.22. While for optical properties, the spectral response showed the current intensity of 11.370 µA which was recorded at the peak wavelength of 880 nm. Therefore, porous GaAs showed good potential and can be used for optoelectronic device applications such as MSM photodetector.

Design and Modelling of Tunnel Field Effect Transistor- using TCAD Modeling

The purpose of this research was to suggest a junction-less strategy for a vertical Tunnel Field Effect Transistor, which would increase the device's efficiency. In this study, we examine the similarities and differences between a negative capacitor TFET and a vertically generated TFET with a source pocket and a heterostructure-based nanowire gate. And how the channel transit impacts the output qualities of a sub-100 nanometer sized device. The Silvaco TCAD (a commercially available tool) was used to simulate a tri-layer high-K dielectric made of hafnium zirconium oxide (HZO) and titanium dioxide (TiO2) materials as gate stacking to the V-TFET and GAA-NC-TFET structures, and the tunnelling and transport parameters were calibrated experimentally. A short bandgap material, GaSb, in the home region to enhance carrier tunnelling via the mentioned three source (GaSb)-channel (Si) heterojunction at varying biases were utilized. Motion, tube length, and saturating velocity are only few of the transport channel characteristics that are investigated. As a result of the building's vertical orientation, the electric field is enhanced, allowing for an ION current of up to 104 Am2. The most unexpected result of this device is that a high ION/IOFF may increase mobility and reduce saturation velocity, perhaps reducing the drain voltage at saturation. The proposed biosensor's sensitivity was multiplied by 108 when vertical and lateral tunnelling were used in tandem. We apply a variety of optimisation strategies to deal with this problem, despite the fact that quantum confinement reduces the effect of mobility variations on device performance. When biomolecules were positively charged, the drain current increased, and when they were negatively charged, the drain current decreased.

Simulation study on the influence of metal contact and MOS interface trap states on the electrical characteristics of SiC IGBT

A 13 kV class n-channel 4H–SiC trench gate insulated gate bipolar transistor (IGBT) structure is designed based on Silvaco TCAD device simulator tool. The influence of metal/SiC and SiC MOS interface trap states on the static and dynamic characteristics of SiC IGBT devices are systematically studied. It is found that the electrical properties of SiC IGBTs are insensitive to the donor or acceptor traps at the interface of metal/SiC and the donor traps at the SiC/SiO2 interface. However, the acceptor traps at the SiC/SiO2 interface affect the electrical properties of SiC IGBTs greatly. When the acceptor trap density at the SiC/SiO2 interface (Dita) is up to the level of 1012 cm−2·eV−1, the turn-on voltage drop (VCEON) is increased gradually with the augmentation of Dita. The breakdown voltage (VBR) of the device is increased slightly. Further study of the device’s turn-off characteristics shows that the turn-off loss (EOFF) is decreased with the increase in Dita but a large tail current is formed. The mechanism may be that when the electrons are injected from the N+ source region into the N− drift region, the SiC/SiO2 interfacial acceptor traps at the side wall of trench gate capture a large number of electrons. As a result, the minority carrier concentration is decreased, and the conductance modulation effect on the N− drift region is weakened.

Simulation study of vertical diamond Schottky barrier diode with field plate assisted junction termination extension

In this paper, we designed vertical diamond Schottky barrier diodes with a field plate assisted junction termination extension (FP-JTE) structure by using Silvaco TCAD. It demonstrates that the JTE structure is more effective to suppress the electric field crowding around the electrode edges than the FP, but it also increases the on-resistance due to the decreasing conduction area. Then, the FP-JTE diamond SBDs are designed to realize the trade-off between the breakdown voltage and on-resistance. It is found that the JTE length should be shorter than the FP to enhance the current conduction, but it needs to cover the cathode edge to suppress the electric field crowding. We also confirm that the FP-JTE SBDs with the JTE length increase from the sidewall toward the center are recommended to take advantage of both FP and JTE structures.

A Fast Recovery SiC TED MOS MOSFET with Schottky Barrier Diode (SBD)

Achieving low conduction loss and good channel mobility is crucial for SiC MOSFETs. However, basic planar SiC MOSFETs provide challenges due to their high density of interface traps and significant gate-to-drain capacitance. In order to enhance the reverse recovery property of the device, a Schottky barrier diode (SBD) was added to the source contact area, the top of the current spreading region, of a trench-etched double-diffused SiC MOS (TED MOS). Two types of SBD structures were optimized to improve the electrical properties using 3D simulation software, “TCAD Silvaco”. During reverse recovery simulation, the carriers of the device were withdrawn from the SBD, indicating that the new design was effective. It also showed that the recovery properties of the new design depended on temperature, carrier lifetime, and the work functions of metals. All the new designs were evaluated in various circumstances to determine the trend. Ultimately, in high-speed switching circuits, the SiC TED MOS with SBD structure efficiently boosted switching speed, while reducing switching loss.

Parametric extraction and internal analysis of fullerene-based polymer bulk heterojunction solar cell

This paper present device model simulation describing the current-voltage characteristics of polymer/fullerene bulk heterojunction solar cell. In the research paper an organic photovoltaic device with PPV/PCBM [poly (2-methoxy-5-{3’,7’-dimethyloctyloxy}-p-phenylene vinylene) and {6,6}- phenyl C61-butyric acid methyl ester] was simulated via Silvaco TCAD 2-D simulation tool. PCBM acts as acceptor and PPV is donor. The models used to simulate the device were Langevin for recombination, s.binding and a.singlet. Simulation of these type of devices is an vital approach to project and predict the cell performance. Under the illumination of one sun (AM 1.5) the simulated organic cell showed a short circuit current density (JSC) of 28 A/m2, open circuit voltage (VOC) of 0.84 Volt and a fill factor (FF) of 52.51%, the resulting maximum efficiency of the PPV/PCBM organic solar cell is 1.22%.

A simulated fabrication and characterization of a 65 nm floating-gate MOS transistor☆

The aim of this study was to virtual fabricate and characterize a Floating-gate MOS transistor of the 65 nm process. The fabrication process was designed and characterized using the TCAD Silvaco tools. In our work, a detailed flow and the parameters are proposed to virtual fabricate the complete Floating-gate MOS transistor, which has extraordinary performances. The MOS has a large timing window of 4 V, a high gate capacitance ratio parameter of 0.645, and a high Write/Erase speed of 50 ms/70 ms. Interestingly, the results are obtained with a thin thickness of 9 nm of a tunnel oxide layer which is smaller than such layer in other works and low supply voltages in which the control gate, drain, and source voltage values are ± 6 V, 1 V, and 1 V, respectively. In addition, our paper presents the effect of the control gate voltage on the performance of the device when it increases from 6 V to 18 V.

Analytical and Numerical Investigation of Nanowire Transistor X-ray Detector

Recently, nanowire detectors have been attracting increasing interest thanks to their advantages of high resolution and gain. The potential of using nanowire detectors is investigated in this work by developing a physically based model for Indium Phosphide (InP) phototransistor as well as by performing TCAD simulations. The model is based on solving the basic semiconductor equations for bipolar transistors and considering the effects of charge distribution on the bulk and on the surface. The developed model also takes into consideration the impact of surface traps, which are induced by photogenerated carriers situated at the surface of the nanowire. Further, photogating phenomena and photodoping are also included. Moreover, displacement damage (DD) is also investigated; an issue arises when the detector is exposed to repeated doses. The presented analytical model can predict the current produced from the incident X-ray beam at various energies. The calculation of the gain of the presented nanowire carefully considers the different governing effects at several values of energies as well as biasing voltage and doping. The proposed model is built in MATLAB, and the validity check of the model results is achieved using SILVACO TCAD device simulation. Comparisons between the proposed model results and SILVACO TCAD device simulation are provided and show good agreement.

Performance analysis of short channel effects immune JLFET with enhanced drive current

AbstractThis manuscript reports analog/RF and noise analysis of a novel junctionless field effect transistor. To reduce the gate induced drain leakage (GIDL), step‐gate‐oxide structure is used with a high‐k buried oxide (BOX) which subsequently reduces IOFF. The off current and gate capacitance is reduced by including step‐gate‐oxide in high k‐BOX JLFET due to increase in the band to band tunneling (BTBT) width. The DIBL is reduced significantly to 0.014 which is 60% less as compared to high‐k BOX JLFET (HB JLFET). For different length and thickness of the step‐gate‐oxide, the analog/RF and noise performance of the step‐gate‐oxide JLFET with high‐k BOX (SGO HB JLFET) have also been investigated in detail. Silvaco TCAD simulation of the proposed structure for 20 nm channel length shows an extremely high ION/IOFF ratio of ~108. The subthreshold swing for the simulated structure was also found to be considerably low (82 mV/dec).

The possibility of gallium oxide (β-Ga2O3) heterojunction bipolar transistors

Bipolar junction transistors have not been viable with β-Ga2O3 due to its poor hole mobility and unavailability of shallow acceptors. Many p-type oxides form high-quality heterojunction diodes (low ideality factor and high breakdown voltage) with β-Ga2O3. We propose using these heterojunctions to make a β-Ga2O3 heterojunction bipolar transistor (HBT). Cu2O/β-Ga2O3 heterojunction is especially promising because of the relatively high electron diffusion length (∼μ m) in Cu2O, a low electron injection barrier at the Cu2O-Ga2O3 interface, and breakdown voltages of >1000 V. Using Silvaco TCAD, we simulate a β-Ga2O3 heterojunction bipolar transistor with a Cu2O base and estimate the power figure of merit (PFOM). We find that the low bandgap of Cu2O severely limits the performance of these HBTs. Reports of Cu2O-Ga2O3 diodes with extremely high breakdown voltage are probably due to heavily doped Cu2O or interface defects, but these effects do not translate to the HBT. For HBTs with PFOM better than the state-of-the-art β-Ga2O3 unipolar transistors, we need alternative p-type oxides with a bandgap E g > 3.4 eV and electron diffusion length >0.4 μ m. We discuss the possible candidates. Using an empirical model for the critical avalanche breakdown field, we estimate the maximum PFOM for possible β-Ga2O3 HBTs.

Design of normally-off p-GaN/AlGaN/GaN heterojunction field-effect transistors with re-grown AlGaN barrier

In this paper, a novel p-GaN/AlGaN/GaN HFET with re-grown AlGaN is designed by using Silvaco TCAD. It demonstrates that a thin AlGaN barrier with relatively small Al content beneath the p-GaN positively shifts the threshold voltage and helps to obtain normally-off operation, while it also degrades the drain current obviously due to the low 2DEG concentration. On the other hand, the re-grown AlGaN barrier in the access regions can recover the 2DEG concentration and enhance the drain current partially. In addition, the field plate structure formed during the AlGaN re-growth process is beneficial to suppress the electric filed crowding and premature breakdown effectively under forward gate bias. By optimizing the device parameters, normally-off p-GaN/AlGaN/GaN HFET with balanced output current, threshold voltage and breakdown voltage is designed.

Abnormal Threshold Voltage Shift and Sub-channel Generation in Top-Gate InGaZnO TFTs under Backlight Negative Bias Illumination Stress

Previous reports on the top-gate IGZO thin-film transistors (TFTs) under negative bias illumination stress (NBIS) show a threshold voltage (VTH) shift to the left. However, in the present study, a right shift in VTH was observed in the reverse-sweep current–voltage (I–V) curves after applying NBIS to top-gate IGZO TFTs by a UV backlight. The hysteresis window of the forward and reverse sweep I–V curves widened with the increase in the stress time. The abnormal VTH shift and hysteresis-window increment are explained using an energy-band diagram. In addition, an abnormal gm peak appeared in the forward I–V curve after 2000 s of the backlight NBIS, which was verified by testing the devices with different dimensions. Silvaco TCAD simulation results indicated a strong electric field in the sidewall, confirming the generation of sub-channels. The comparison of the ΔVTH after UV backlight NBIS in three different devices suggested that the higher N2O/SiH4 flow rate and lower power deposition can produce a good quality buffer layer. A rapid examination of a buffer layer is possible using the backlight NBIS. In addition, the presence of H2 in the buffer layer was confirmed by the thermal desorption spectroscopy. Finally, the reliability of the devices can be enhanced by improving the modulation of the existing deposition process.

Modeling and Performance Analysis of a Split-Gate T-Shape Channel DM DPDG-TFET Label-Free Biosensor

This article proposes, for the first time, a split-gate T-shape channel dielectrically modulated (DM) double-gate TFET (DGTFET) with a drain pocket (DP). This device can be used as a label-free biosensor. The analytical model for DM DPDG-TFET has been developed and it has been validated against commercial simulation software (Silvaco TCAD). This article intends to focus both on the sensitivity of the biosensor and its performance as a tunnel field-effect transistor (TFET) device. This has been accomplished by improvisations in the channel shape. The performance of the device has thoroughly been investigated in terms of threshold voltage, subthreshold slope, ON current, and OFF current. Due to the novel design, the proposed TFET possesses higher sensitivity, higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ {\text{ON}}}/{I}_{ {\text{OFF}}}$ </tex-math></inline-formula> current ratio, and lower subthreshold slope. The inclusion of DP at the drain–channel junction proves to be a successful way to remove the ambipolarity completely. The high ON current without any ambipolarity has been achieved by optimizing the DP length and its doping concentration. The proposed T-shape DM DPDGTFET proves itself to be superior to several reported devices in terms of both biosensor as well as field-effect transistor (FET) device. The presence and absence of charge of various biomolecules are taken into consideration for evaluation of device sensitivity as a label-free biosensor.

Study of GaN/AlGaN air structure gate HEMTs with high linearity for RF applications

The effect of a novel float gate HEMT with Gan cap under the gate is studied, its DC and RF characteristics have been shown by using SILVACO TCAD tool, as contrast, the simulation of the conventional T shape gate hemt, which fitting well with the experimental result, is also demonstrated. The proposed structure offers approximately 5 times improvement in power gain cutoff frequency (fmax) and current gain Cut-off frequency(fT) (from 5.68 and 3.7 GHz to 30.1 and 20.1 GHz, respectively.) and it greatly enhances the linearity of the Gan based HEMT, a much flatter curve for fT/fmax versus gate voltage are also shown, and 1 V positive threshold voltage shift is gained, meanwhile the off-state drain leakage current is also improved to a certain extend, therefor the hemt obtains a much higher Ion/Ioff ratio, without sacrificing the saturate current. Besides, the degradation of drain current due to the self-heating effect is also ameliorated by applying the novel structure. Finally, the corresponding electrical characteristic changes are systematically analyzed according to the energy band and other schematic diagrams, the physical insight is given in explaining the mechanism inside.

Ge‐ and Ge1−zSnz‐Based Gate‐Underlap Dual Material Double Gate Tunnel Field Effect Transistor: Modeling, Optimization, and its Application to Biosensors

Herein, an n‐channel dual material double gate tunnel field effect transistor (DMDG‐TFET) with a gate–drain underlap using Ge and Ge1−zSnz is proposed. An analytical model has been developed to optimize the length of the underlap region for Ge and Ge–Sn alloy as the channel material. The ambipolarity shown by TFET has been utilized to perform a label‐free biosensing in response to the change of permittivity of the biomaterials used in the gate–drain underlap region. The use of Ge–Sn alloy as a channel material results in a lower ambipolar current but higher sensitivity to the presence of biomolecules. DMDG with workfunction (4 and 4.4 eV) is used to optimize the device performance. The analytical results have been validated by the results obtained using commercial software (Silvaco TCAD). A high sensitivity of the biosensor device is obtained by utilizing the tunnel FET ambipolar current with optimized gate underlap of LUD = 55 nm (for Ge) and LUD = 38 nm (for Ge–Sn alloy).

Superior efficiency for homojunction GaAs solar cell

This research presents a simulation study to achieve an optimized homojunction GaAs solar cell using SILVACO TCAD. A solar cell with configuration of p+ -AlGaAs as window, p-GaAs as emitter, n-GaAs as base and n+ -AlGaInP as BSF layer is proposed. The AlGaInP is selected as BSF layer due to high bandgap as compared to AlGaAs that is usually used in literature. Large scale of variation for doping concentration and thickness for all layers of cell have been simulated. The results show an improvement for solar cell parameters for the optimized cell as compared with the proposed one, where Jsc increases from 40.03 mA/cm2 to 52.58 mA/cm2 , Voc slightly increases from 0.94 V to 1 V, Pmax increases from 30.8 mW/cm2 to 46.86 mW/cm2 , FF increases from 82.19% to 88.54% and η increases from 22.29% to 33.94%. Which confirms the effectiveness of the doping concentration and thickness on solar cell performance.

Fabrication of high-performance dual-gate ISFET pH sensors using In2O3 nano-channel

Here, a high-performance dual-gate ionsensitive field-effect transistor (ISFET) was designed for pH detection based on the high carrier mobility and chemical stability of In2O3. To optimize the structural parameters of the ISFET, the ISFET model with a dual-gate structure was constructed using the Silvaco TCAD. The effects of the channel layer and gate dielectric layer parameters on the performance of the ISFET model were investigated in the dual-gate structure. Following the optimal parameters of the simulation, the dual-gate ISFET chip was fabricated by microfabrication techniques. The pH sensitivity of the fabricated chip was 321.54 mV/pH and exhibited good stability with low drift and hysteresis voltage. In addition, we also tested the pH change caused by the hydrogen peroxide oxidation reaction under catalysis by horseradish peroxidase. The sensitivity was up to 103.28 µA/mM, verifying this high-performance ISFET can be used to detect pH changes of trace substances in the biosensing field.