Silicon Interface Research Articles

Extension of Far UV spectroscopic ellipsometry studies of High-κ dielectric films to 130 nm

Next generation CMOS devices use a high-κ dielectric layer (HfO2, HfSiO, HfSiON and La2O3) grown on thin interfacial silicon dioxide as the gate dielectric. The higher dielectric constant of the Hf oxide based film stack allows a decrease in equivalent oxide thickness (EOT). Because the high-κ film stack has a greater physical thickness than an electrically equivalent SiO2 film, the tunneling current decreases. It is a critical metrology requirement to measure the thickness of silicon dioxide and high-κ film stacks. Spectroscopic ellipsometry (SE) in the far UV wavelength region can be used to differentiate the high-κ films from silicon dioxide. This is due to the non-zero nature of the imaginary part of the dielectric function (beyond 6eV) in the far UV region for high-κ films. There has been some conjecture that optical studies should be extended beyond 150nm further into the VUV. This study addresses these concerns through determination of the dielectric function down to 130nm. We show the fitted dielectric function of hafnium silicates and lanthanum oxide down to 130nm. X-ray reflectivity (XRR) measurements were also performed on the high-κ films to complement the thickness measurements performed with SE.

A comprehensive structural analysis of silicon carbide layers grown by vacuum epitaxy on silicon from hydrides and hydrocarbons

The phase composition, surface morphology and crystalline structure of carbon-containing silicon layers grown on silicon plates of various orientation by vacuum gas phase epitaxy using different operating conditions are considered. The possibility of phase transition from a Si1−xCx solid solution to silicon carbide upon annealing of the structures obtained by low-temperature epitaxy is discussed. The films were examined by the electron, probe and interference optical microscopy, electron diffractometry, and X-ray diffraction methods. The effect of germanium intercalated in a film during its growth on the surface morphology and crystalline structure of carbon-containing silicon layers is examined. Irrespective of the method of germanium insertion in the growing film, a maximum Ge concentration is attained at the interface of silicon and 3C-SiC layers. A comparative study of the surface roughness of 3C-SiC films grown on Si(100) was performed upon variation of the temperature and germanium content in a mixture of gases. The interference optical microscopy was used to investigate the surface morphology of heteroepitaxial structures 3C-SiC/Si in comparison with the surface characteristics of buffer structures based on Si and Ge. The 3C-SiC layers grown on Si(100) and Si(110) were shown to have quite a low surface roughness, which is comparable with the characteristics of Si1−xGex/Si(100) layers and CP(Ge-Si1−xGex)/Si(100) superlattices at the initial roughness of Si underlayers ∼1–2 nm.

Limitations of Field Plate Effect Due to the Silicon Substrate in AlGaN/GaN/AlGaN DHFETs

We investigated the limitations of the field plate (FP) effect on breakdown voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> that is due to the silicon substrate in AlGaN/GaN/AlGaN double heterostructures field-effect transistors. In our previous work, we showed that in devices with large gate-drain distance (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> > 8 μm), the breakdown voltage does not linearly increase with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> because of a double leakage path between the silicon substrate and the metal contacts, which makes the device break at the silicon interface. In this paper, we showed that the effect of the FP for such large <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> is not significant because the breakdown is still dominated by the silicon substrate. The increase in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> due to the FP is significant only for devices with small gate-drain distances ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> <; 8 μm). Indeed we show that for such small <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> the increase in the breakdown voltage is more than double, whereas for larger <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> , this is only about 10%. Simulations of AlGaN/GaN/AlGaN devices for small <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> are carried out with different FP lengths and passivation thickness in order to study the electric field distribution.

The silane depletion fraction as an indicator for the amorphous/crystalline silicon interface passivation quality

In silicon heterojunction solar cells, thin amorphous silicon layers passivate the crystalline silicon wafer surfaces. By using in situ diagnostics during plasma-enhanced chemical vapor deposition (PECVD), the authors report how the passivation quality of such layers directly relate to the plasma conditions. Good interface passivation is obtained from highly depleted silane plasmas. Based upon this finding, layers deposited in a large-area very high frequency (40.68 MHz) PECVD reactor were optimized for heterojunction solar cells, yielding aperture efficiencies up to 20.3% on 4 cm2 cells.

Development, Optimization and Evaluation of a CF4 Pretreatment Process to Remove Unwanted Interfacial Layers in Stacks of CVD and PECVD Polycrystalline Silicon-Germanium for MEMS Applications

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work we demonstrate a technique of removing unwanted interfacial (silicon-) germanium oxide layers that form on the surface of SiGe depositions as soon as the wafers are removed from the deposition chamber and exposed to an O2 ambient.

Thermal Stability Improvement of the Lanthanum Aluminate/Silicon Interface Using a Thin Yttrium Interlayer

We investigate the effects of an ultrathin yttrium interlayer at the interface of lanthanum aluminate and silicon with thermal annealing. Addition of the yttrium interlayer resulted in a smaller increase in the valence band offset, a reduction in the interface trap density, and a close to four-order reduction in leakage current after thermal annealing. The valence band offsets are measured with X-ray photoelectron spectroscopy and compared with those obtained from electrical measurements. The good correlation of the two measurements indicates a change in the valence band offset caused by interface dipoles. The performance improvements are attributed to a reduction in lanthanum interdiffusion and the formation of an yttrium-rich silicate interfacial layer, which minimize leakage current flow and reduce hydrogen desorption in interface trap formation.

Investigation of a‐Si (N+)/c‐Si (P) hetero‐junction solar cell through AFORS‐HET simulation

AbstractIn this paper, a TCO/a‐Si(N+)/a‐Si(i)/c‐Si(P)/Al‐BSF(P+) structure hetero‐junction (HJ) cell model is developed. With AFORS‐HET V3.0, we investigate the influence of amorphous silicon (a‐Si) emitter and amorphous silicon (a‐Si)/crystalline silicon (c‐Si) interface defects on the HJ cell performance. Through modulating a‐Si(N+) emitter doping concentration and band offset at a‐Si/c‐Si interface, a maximum width value of 103 nm inversion layer is observed in the c‐Si(P) side. For 1 Ω.cm c‐Si (P) substrate, emitter doping of over 1 × 1020 cm−3 is necessary for achieving a high‐efficiency a‐Si/c‐Si HJ cell. Furthermore, defects at a‐Si(N+)/c‐Si(P) interface severely affect the open circuit voltage (Voc) and short circuit current density (Jsc) of the cell. Meanwhile, simulation indicates that Voc is more sensitive to interface defect density (Dit) than Jsc. A thin a‐Si(i) layer between a‐Si(N+) and c‐Si(P) does induce great improvement in Voc of TCO/a‐Si(N+)/a‐Si(i)/c‐Si(P)/Al‐BSF(P+) cell. As a result, high cell efficiency of 22.27% is achieved for a‐Si(N+)/c‐Si(P) HJ Cell with optimized parameters. Copyright © 2010 John Wiley &amp; Sons, Ltd.

Circular Geometry Transistors Fabricated on Germanium-on-Alumina Bonded Substrates

Germanium (Ge) has been bonded to fine grain alumina (Al2O3) by means of a polished polycrystalline silicon interface layer. After room temperature bonding and subsequent bond strength annealing at 150 oC for 24 hrs, the germanium layer was ground and polished to 100µm. Low temperature Tungsten (W) gate circular geometry devices, W/L = 9, fabricated on this layer exhibited effective mobility values of 150 cm2/Vs. This is much lower than results obtained on equivalent devices on bulk Ge. Improvement in the germanium polish process resulted in transistors with an effective mobility of 415 cm2/Vs, comparable to that of the bulk Ge devices. Low temperature measurement, down to temperatures of 173 K, showed an improvement in device performance resulting in both an increase in effective mobility to 591 cm2/Vs and a decrease in sub threshold slope from 180 mV/dec to 60 mV/dec indicating a reduction in leakage current.

Role of hydrogen in the surface passivation of crystalline silicon by sputtered aluminum oxide

AbstractAluminum oxide films can provide excellent surface passivation on both p‐type and n‐type surfaces of silicon wafers and solar cells. Even though radio frequency magnetron sputtering is capable of depositing aluminum oxide with concentrations of negative charges comparable to some of the other deposition methods, the surface passivation has not been as good. In this paper, we compare the composition and bonding of aluminum oxide deposited by thermal atomic layer deposition and sputtering, and find that the interfacial silicon oxide layer and hydrogen concentration can explain the differences in the surface passivation. Copyright © 2010 John Wiley &amp; Sons, Ltd.

Through Silicon Via (TSV) defect investigations using lateral emission microscopy

Infra-red photoemission microscopy has been applied for the localization of defects in 3D integrated circuits containing Through Silicon Vias (TSVs). For these investigations, the familiar (planar) emission microscopy configuration was extended to allow imaging and emission microscopy on vertical TSV sidewalls, from versatile 3D viewpoints. Flexible viewing orientation was achieved by introducing an additional reflecting surface into the optical path. Precise alignment of the angle of incidence at the air–silicon interface, with sufficient accuracy to ensure no problematic refraction-related errors, was possible using this experimental set-up. Three examples are presented, showing defect localizations and underlying physical leakage mechanisms in TSV structures.

Computational Studies of Surfaces and Interfaces of Silicon as Li-Ion Battery Anodes

not Available.

X-ray spectroscopic examination of thin HfO2 films ALD- and MOCVD-grown on the Si(100) surface

HfO2 films 5 nm thick grown on Si(100) substrates by the methods of MOCVD hydride epitaxy and atomic layer deposition (ALD) are studied using X-ray photoelectron spectroscopy combined with Ar+ ion etching and X-ray reflectometry. It is found that (i) the ALD-grown HfO2 films are amorphous, while the MOCVD-grown films show signs of a crystal structure; (ii) the surface of the ALD-grown films is more prone to contamination and/or is more reactive; and (iii) the amount of interfacial silicon dioxide in the case of the MOCVD-grown film is greater than in the case of the films synthesized by ALD. It is also shown that the argon ion etching of the HfO2 film results in the formation of a metallic hafnium layer at the interface. This indicates that HfO2 can be used not only as a gate dielectric but also as a material suitable for fabricating nanodimensional conductors by direct decomposition.

Passivation of Si(111) surfaces with electrochemically grafted thin organic films

Ultra thin organic films (about 5 nm thick) of nitrobenzene and 4-methoxydiphenylamine were deposited electrochemically on p-Si(111) surfaces from benzene diazonium compounds. Studies based on atomic force microscopy, infrared spectroscopic ellipsometry and x-ray photoelectron spectroscopy showed that upon exposure to atmospheric conditions the oxidation of the silicon interface proceed slower on organically modified surfaces than on unmodified hydrogen passivated p-Si(111) surfaces. Effects of HF treatment on the oxidized organic/Si interface and on the organic layer itself are discussed.

Nearly Massless Electrons in the Silicon Interface with a Metal Film

We demonstrate the realization of nearly massless electrons in the most widely used device material, silicon, at the interface with a metal film. Using angle-resolved photoemission, we found that the surface band of a monolayer lead film drives a hole band of the Si inversion layer formed at the interface with the film to have a nearly linear dispersion with an effective mass about 20 times lighter than bulk Si and comparable to graphene. The reduction of mass can be accounted for by a repulsive interaction between neighboring bands of the metal film and Si substrate. Our result suggests a promising way to take advantage of massless carriers in silicon-based thin-film devices, which can also be applied to various other semiconductor devices.

The Effect of Doping Concentration of Si on the Nature of Barrier of Co$_{2}$MnSi/MgO/n-Si Junctions

In this work, we have presented the electrical characteristic of CoMnSi/MgO/n-Si junctions as a function of the doping concentration of Si. Films were fabricated by dc sputtering and post annealed at 400°C for 1 h without breaking the vacuum. The CoMnSi/MgO/n-Si junctions exhibited diode like characteristics at low doping concentration 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> /cc. This can be attributed due to oxide charges or interface traps close to the silicon interface, which causes the bend bending and forms the large extended depletion region. The junction characteristic was found to change with the increase of doping concentration and became symmetric at doping concentration of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> / <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> . Therefore, with the same thickness of MgO barrier, the junction characteristic was changed from Schottky to symmetric tunneling with the doping density of Si. The origin of the change of junction characteristic might be due to the change of the depletion width with the doping density.

Influence of oxygen on the sputtering of aluminum oxide for the surface passivation of crystalline silicon

While sputtering has been shown to be capable of depositing aluminum oxide suitable for surface passivation, the mechanisms for this are yet to be firmly established and its potential realized. In this paper, we investigate the relationships between the oxygen in the sputtering process to the resulting composition of the deposited film and the surface passivation obtained. We find that surface passivation is not strongly dependent on the bulk composition of the film. Instead the results indicate that the interfacial silicon oxide layer that forms after annealing between the aluminum oxide film and the silicon is a much more important factor; it is this combined structure of aluminum oxide, silicon oxide and silicon that is crucial for obtaining negative charges and excellent surface passivation.

Photoemission study of the SiO2 conversion mechanism to magnesium silicate

The objective of this work is to investigate interface chemistries which minimize the interfacial silicon oxide transition region at Si/high-k dielectric interfaces. We report on the mechanism by which a silicon native oxide layer is converted into magnesium silicate. The deposition of metal Mg onto a SiO2 native oxide surface resulted in the formation of a magnesium silicide in addition to substochiometric silicon oxides and a significant decrease in the oxidised silicon signal. Annealing to 300 °C resulted in the decomposition of the magnesium silicide, oxidation of the Mg, and the desorption of excess metallic Mg. Subsequent annealing to 500 °C resulted in converting the SiO2 into magnesium silicate. The results suggest that the decomposition of the Mg silicide in the presence of the residual native oxide facilitates silicate formation at 500 °C. Due to the reported thermal stability of Mg silicate it is suggested that this process may be beneficial in modifying the interface characteristics of the Si/high-k dielectric interface which has potentially significant implications for future semiconductor device generations.

Surface passivation of III–V semiconductors for future CMOS devices—Past research, present status and key issues for future

Currently, III–V metal–insulator–semiconductor field effect transistors (MISFETs) are considered to be promising device candidates for the so-called “More Moore Approach” to continue scaling CMOS transistors on the silicon platform. Strong interest also exists in III–V nanowire MISFETs as a possible candidate for a “Beyond CMOS”-type device. III–V sensors using insulator–semiconductor interfaces are good candidates for “More Moore”-type of devices on the Si platform. The success of these new approaches for future electronics depends on the availability of a surface passivation technology which can realize pinning-free, high-quality interfaces between insulator and III–V semiconductors. This paper reviews the past history, present status and key issues of the research on the surface passivation technology for III–V semiconductors. First, a brief survey of previous research on surface passivation and MISFETs is made, and Fermi level pinning at insulator–semiconductor interface is discussed. Then, a brief review is made on recent approaches of interface control for high-k III–V MIS structures. Subsequently, as an actual example of interface control, latest results on the authors’ surface passivation approach using a silicon interface control layer (Si ICL) are discussed. Finally, a photoluminescence (PL) method to characterize the interface quality is presented as an efficient contactless and non-destructive method which can be applied at each step of interface formation process without fabrication of MIS capacitors and MISFETs.

Controlling cellular activity by manipulating silicone surface roughness

Silicone elastomers exhibit a broad range of beneficial properties that are exploited in biomaterials. In some cases, however, problems can arise at silicone elastomer interfaces. With breast implants, for example, the fibrous capsule that forms at the silicone interface can undergo contracture, which can lead to the need for revision surgery. The relationship between surface topography and wound healing – which could impact on the degree of contracture – has not been examined in detail. To address this, we prepared silicone elastomer samples with rms surface roughnesses varying from 88 to 650 nm and examined the growth of 3T3 fibroblasts on these surfaces. The PicoGreen ® assay demonstrated that fibroblast growth decreased with increases in surface roughness. Relatively smooth (∼88 nm) PDMS samples had ca. twice as much fibroblast DNA per unit area than the ‘bumpy’ (∼378 nm) and very rough (∼604 and ∼650 nm) PDMS samples. While the PDMS sample with roughness of ∼650 nm had significantly fewer fibroblasts at 24 h than the TCP control, fibroblasts on the smooth silicone surprisingly reached confluence much more rapidly than on TCP, the gold standard for cell culture. Thus, increasing the surface roughness at the sub-micron scale could be a strategy worthy of consideration to help mitigate fibroblast growth and control fibrous capsule formation on silicone elastomer implants.

Optimization of moth‐eye antireflection schemes for silicon solar cells

AbstractNanostructured moth‐eye antireflection schemes for silicon solar cells are simulated using rigorous coupled wave analysis and compared to traditional thin film coatings. The design of the moth‐eye arrays is optimized for application to a laboratory cell (air–silicon interface) and an encapsulated cell (EVA‐silicon interface), and the optimization accounts for the solar spectrum incident on the silicon interface in both cells, and the spectral response of both types of cell. The optimized moth‐eye designs are predicted to outperform an optimized double layer thin film coating by approximately 2% for the laboratory cell and approximately 3% for the encapsulated cell. The predicted performance of the silicon moth‐eye under encapsulation is particularly remarkable as it exhibits losses of only 0·6% compared to an ideal AR surface. Copyright © 2010 John Wiley &amp; Sons, Ltd.