Silicon Sidewall Research Articles

Flow-through microfluidic relative permittivity sensor using highly-doped silicon sidewall electrodes

Abstract This paper reports a flow-through sensor for the real-time measurement of the relative permittivity of a flowing fluid. The proposed sensor contains multiple parallel microchannels. Each channel acts as a parallel plate capacitor in which the electrodes are isolated from the fluid. This approach results in a low pressure drop and high sensitivity while the internal volume is only 50 nl. The fabrication technology allows for controllable scaling of the channel geometry. Equally deep microchannels with widths varying between 5 µm and 50 μ m are fabricated. The fabrication technology is compatible with other flow-through sensors, enabling further on-chip integration. The sensor has been characterised using 10 different fluids with relative permittivity values ranging from 1 to 80—including water and water-containing mixtures—at a measurement frequency of 300 kHz. The results show an accuracy within 3% of full scale and the repeated measurements with nitrogen and water show standard deviations of 1.20 and 1.03, respectively.

Design and Architecture Definition for Advanced 3D Fan-Out Wafer-Level Packaging

Advanced 2.5D/3D wafer-level fan-out packaging technologies have been studied widely in literature and industry in recent years. Miniaturization, reduction in manufacturing costs, improvement in performance, and lower power consumption using packaging technologies drive increase in interconnect density and pitch scaling. Heterogeneous systems in package used in advanced packaging often include a combination of silicon, epoxy underfill or mold compounds, and organic or inorganic passivation or redistribution layers. This heterogeneity poses challenges with manufacturability, process selection, package architecture, and test vehicle design. The coefficient of thermal expansion mismatch, wafer warpage, and wafer yield are some of the critical process challenges. Delamination of silicon side wall or passivation to epoxy underfill or mold compound, joint fatigue are critical reliability challenges. This article explores various processes and reliability challenges with 3D wafer-level fan-out packaging and provides package design and architecture guidelines to overcome these failure modes. Stacked die-to-wafer test vehicles have been used for data collection. Different assembly materials, processes, and tooling have been evaluated to define comprehensive design rules.

Thin and Ultra-thin Sidewall Protected P-WLCSP

Diversity in packaging for a strong supply chain requires higher performance and lower cost processes for new manufacturers. Six-side protected, aka “6S or fully protected”, CSP is an emerging and rapidly growing market. Fully protected CSP (without substrates or lead-frames) was first implemented with processes such as M-series and eWLB. These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations most common to FO to obtain 6-side die protection. These steps can be eliminated in a wafer level process to provide high-performance low-cost P-WLCSP to enable new CSP manufacturing capability, Fan-In and Chiplets. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected CSP, fan-in, and chiplets. Protected FI process innovations can improve performance in power devices, RF switches, photonic IC (PIC), die stacking, and thin board applications. This paper builds on the SoP-TM process development provided at the IMAPS Symposium earlier this year with the addition of first silicon data for electrical test chips. SoP-TM test chip features include 10um silicon thickness, metal interconnect and micro-bumps, smooth silicon sidewalls and 6-side polyimide encasement. Reliability data and testing is a key area of investigation for thin-device technology. Ultra-thin device reliability test methods under consideration for new NIST standards will be presented. Mechanical, high temperature and high humidity reliability for SoP-TM test chips, Chip-on-Flex (COF) and Flip Chip using the new test methods will be presented.

Monolithic SOI through-wafer Knudsen pumps with mechanically robust Si channels

Knudsen pumps (KPs) generate gas flow using thermal transpiration in narrow channels with a longitudinal temperature gradient. With no moving parts, KPs offer long lifetime and are attractive for complex microfluidic systems. Although high performance was previously reported in microfabricated KPs that utilized suspended dielectric membranes to construct the pumping channels, this approach can limit the mechanical robustness and complicate the fabrication process. In this work, we present monolithically microfabricated KPs without using suspended membranes. These types of structures significantly improve the mechanical robustness, allow a wider process window, and simplify the microfabrication process. The pumping channels in this work are 14 µm in length, 1.2 × 200 µm2 in cross-section, vertically oriented, and with rigid silicon and dielectric sidewalls; the overall structures are easily manufacturable. This work primarily focuses on two core KP designs, which incorporate 4 and 6 parallel pumping channels in ≈ 11 and 17 mm2 footprints, respectively. The scaling capability is also investigated preliminarily in a design with 45 parallel pumping channels. The KPs were fabricated on a silicon-on-insulator wafer by a six-mask lithographic process with standard fabrication steps. This process eliminated the use of complicated trench refill, polish, and sacrificial dry etch steps that were required for the previously reported KPs with suspended membranes. At atmospheric pressure, the 4-channel KPs provided a blocking pressure of 620 Pa and maximum flow rate of 0.041 sccm through 0.001 mm2 channel area, using 2 W applied power. This maximum flow rate per unit channel area (sccm/mm2) is superior to that of the KPs with suspended membranes. For all the KP designs, the experimentally measured pumping performance well matched the modeling results, with <15 % discrepancy. The fabrication simplicity and reliability of the mechanically robust KPs can enable monolithic integration onto complex lab-on-a-chip systems.

Effects of C4F8 plasma polymerization film on etching profiles in the Bosch process

The Bosch process is a deep etching method for silicon that uses C4F8 plasma-deposited polymerized films as passivation films to protect the silicon sidewalls. This study measured the deposition rate of the passivation films and the etch rate with F-radical exposure and analyzed the chemical composition of the films. Additionally, we observed the deformation of the passivation films during the Bosch process and assessed its influence on the etch profiles. As the C4F8 flow rates increased, the deposition rates attained a local maximum, subsequently decreased to a local minimum and then increased again. The deposition rates were extremely low when the pressure exceeded 10 Pa. With the increasing C4F8 flow rates, inductively coupled plasma power, and pressure, the respective bond content varied up to 10%, and C—CFX and C—C bond contents were replaced with CF2 and CF contents, respectively. The results indicated that the chemical composition of the films did not affect the etch rates of the films, and upon exposure to F radicals, the chemical composition of all films transformed into an identical chemical composition with a higher CF2 bond content. Polymerized films with low CF2-bond content deformed with F-radical exposure, enabled the passage of F radicals, and did not serve as passivation films. In addition to high deposition rates and high F-radical resistance, the Bosch process requires passivation films with high CF2 bond content. The present findings will aid in tuning the parameters of the Bosch process and increase the productivity of silicon deep reactive-ion etching.

Roughness Suppression in Electrochemical Nanoimprinting of Si for Applications in Silicon Photonics

Metal-assisted electrochemical nanoimprinting (Mac-Imprint) scales the fabrication of micro- and nanoscale 3D freeform geometries in silicon and holds the promise to enable novel chip-scale optics operating at the near-infrared spectrum. However, Mac-Imprint of silicon concomitantly generates mesoscale roughness (e.g., protrusion size≈45nm) creating prohibitive levels of light scattering. This arises from the requirement to coat stamps with nanoporous gold catalyst that, while sustaining etchant diffusion, imprints its pores (e.g., average diameter≈42nm) onto silicon. In this work, roughness is reduced to sub-10nm levels, which is in par with plasma etching, by decreasing pore size of the catalyst via dealloying in far-from equilibrium conditions. At this level, single-digit nanometric details such as grain-boundary grooves of the catalyst are imprinted and attributed to the resolution limit of Mac-Imprint, which is argued to be twice the Debye length (i.e., 1.7nm)-a finding that broadly applies to metal-assisted chemical etching. Last, Mac-Imprint is employed to produce single-mode rib-waveguides on pre-patterned silicon-on-insulator wafers with root-mean-square line-edge roughness less than 10nm while providing depth uniformity (i.e., 42.9±5.5nm), and limited levels of silicon defect formation (e.g., Raman peak shift<0.1cm-1 ) and sidewall scattering.

The initial run-in and long-term drift of the adhesive force between polycrystalline silicon MEMS sidewalls

In this paper we measure the evolution of adhesion between two polycrystalline silicon sidewalls of a microelectromechanical adhesion sensor during three million contact cycles. We execute a series of AFM-like contact force measurements with comparable force resolution, but using real MEMS multi-asperity sidewall contacts mimicking conditions in real devices. Adhesion forces are measured with a very high sub-nanonewton resolution using a recently developed optical displacement measurement method. Measurements are performed under well-defined, but different, low relative humidity conditions. We found three regimes in the evolution of the adhesion force. (I) Initial run-in with a large of cycle-to-cycle variability, (II) Stability with low variability, and (III) device-dependent long term drift. The results obtained demonstrate that although a short run-in measurement shows stabilization, this is no guarantee for long-term stable behavior. Devices performing similarly in region II, can drift very differently afterwards. The adhesion force drift during millions of cycles is comparable in magnitude to the adhesion force drift during initial run-in. The boundaries of the drifting adhesion forces are reasonably well described by an empirical model based on random walk statistics. This is useful knowledge when designing polycrystalline silicon MEMS with contacting surfaces.

Unprotected sidewalls of implantable silicon-based neural probes and conformal coating as a solution

Silicon-based implantable neural devices have great translational potential as a means to deliver various treatments for neurological disorders. However, they are currently held back by uncertain longevity following chronic exposure to body fluids. Conventional deposition techniques cover only the horizontal surfaces which contain active electronics, electrode sites, and conducting traces. As a result, a vast majority of today’s silicon devices leave their vertical sidewalls exposed without protection. In this work, we investigated two batch-process silicon dioxide deposition methods separately and in combination: atomic layer deposition and inductively-coupled plasma chemical vapor deposition. We then utilized a rapid soak test involving potassium hydroxide to evaluate the coverage quality of each protection strategy. Focused ion beam cross sectioning, scanning electron microscopy, and 3D extrapolation enabled us to characterize and quantify the effectiveness of the deposition methods. Results showed that bare silicon sidewalls suffered the most dissolution whereas ALD silicon dioxide provided the best protection, demonstrating its effectiveness as a promising batch process technique to mitigate silicon sidewall corrosion in chronic applications.

Heavily-Doped Bulk Silicon Sidewall Electrodes Embedded between Free-Hanging Microfluidic Channels by Modified Surface Channel Technology.

Surface Channel Technology is known as the fabrication platform to make free-hanging microchannels for various microfluidic sensors and actuators. In this technology, thin film metal electrodes, such as platinum or gold, are often used for electrical sensing and actuation purposes. As a result that they are located at the top surface of the microfluidic channels, only topside sensing and actuation is possible. Moreover, in microreactor applications, high temperature degradation of thin film metal layers limits their performance as robust microheaters. In this paper, we report on an innovative idea to make microfluidic devices with integrated silicon sidewall electrodes, and we demonstrate their use as microheaters. This is achieved by modifying the original Surface Channel Technology with optimized mask designs. The modified technology allows to embed heavily-doped bulk silicon electrodes in between the sidewalls of two adjacent free-hanging microfluidic channels. The bulk silicon electrodes have the same electrical properties as the extrinsic silicon substrate. Their cross-sectional geometry and overall dimensions can be designed by optimizing the mask design, hence the resulting resistance of each silicon electrode can be customized. Furthermore, each silicon electrode can be electrically insulated from the silicon substrate. They can be designed with large cross-sectional areas and allow for high power dissipation when used as microheater. A demonstrator device is presented which reached at a power of , limited by thermal conduction through the surrounding air. Other potential applications are sensors using the silicon sidewall electrodes as resistive or capacitive readout.

Ultra-wideband far-infrared absorber based on anisotropically etched doped silicon.

Far-infrared absorbers exhibiting wideband performance are in great demand in numerous applications, including imaging, detection, and wireless communications. Here, a nonresonant far-infrared absorber with ultra-wideband operation is proposed. This absorber is in the form of inverted pyramidal cavities etched into moderately doped silicon. By means of a wet-etching technique, the crystallinity of silicon restricts the formation of the cavities to a particular shape in an angle that favors impedance matching between lossy silicon and free space. Far-infrared waves incident on this absorber experience multiple reflections on the slanted lossy silicon side walls, being dissipated towards the cavity bottom. The simulation and measurement results confirm that an absorption beyond 90% can be sustained from 1.25 to 5.00 THz. Furthermore, the experiment results suggest that the absorber can operate up to at least 21.00 THz with a specular reflection less than 10% and negligible transmission.

Influence of operation parameters on BOSCH-process technological characteristics

Authors investigated direct plasmachemical etching of silicon with Bosch-process using installation for inductively coupled plasma (PLATRAN-100) in gas area consist of SF6 and CHF3 gases in etching and deposition steps respectively. Defined correlations of etching rate, selectivity Si/photoresist, anisotropy, etch uniformity and sidewall angle on flow rate of polymerizing gas and electrical bias on deposition step. It is shown that increasing of CHF3 flow rate leads to higher etch selectivity Si/photoresist, anisotropy and uniformity of silicon but increase etching rate and sidewall angle. Also there was demonstrated that increasing of electrical bias on deposition step leads to higher silicon etching rate, uniformity and sidewall angle but at the same time decrease anisotropy and selectivity Si/photoresist. Authors reached etch selectivity Si/photoresist about 38 with etch uniformity 99.3% and depth about 18 mkm. The highest speed of silicon etch was 3.12 μm/min with uniformaty 99.7% and sidewall angle 89.6 °.

Adjustable Silicon Corner Rounding Radius by Wet Technique

Shallow trench isolation (STI) and active area (AA) top corner rounding is important to devices performance. AA top corner rounding techniques include STI etch, linear oxidation , H2 annealing and wet oxide pull back (PB). However, conventional STI etch will caused AA facet and need to additional thermal in linear oxidation or H2 annealing processes. Wet oxide PB is easily to control the pad oxide etching amount and reach desired AA top corner top rounding radius.In this study, different pad oxide PB amount by Hydrogen Fluoride (HF) with corner rounding correlation were shown. At high pad oxide PB amount, additional hydrogen peroxide (H2O2) with dilute HF can optimize the AA top corner profile and enlarge the corner radius. Sharp AA corners profile caused gate oxide formation thickness thinning let strong electrical filed at AA corner. In wafer acceptable test had brought about double hump effect in I-V characteristics and inverse narrow width effect. Pad oxide PB following STI Etch is used by HF to let the silicon top corner be exposed and beneficial for increasing AA top corner rounding radius of liner oxidation process. This study gives some course to improve the silicon corner profile and AA top corner radius. After STI etch process, different wet etch amount were used for pad oxide PB from pad nitride by 0.49% HF process time adjustment. Different wet oxide PB amount were split for corner radius comparison. As oxide PB amount increased from 0nm to 5nm the corner radius can be improved, and the best radius showed at PB 5nm. When oxide PB amount add to 7.5nm, the corner radius became worse slightly. The radius of PB 10nm is even worse and close to without oxide PB process. This result suspected that AA corner profile might be changed in wet oxide PB process. When oxide PB amount increase, oxide etch rate might decrease and exposed silicon corner be continually damaged by HF erosion. The silicon damage of PB 5nm is slight and can be recovered after linear oxidation thermal process. At PB 7.5nm the AA corner “stepped” profile was observed. It can explain while the PB amount >5nm the corner rounding radius decrease. Because the “stepped” profile caused the corner split two curvatures then the radius decrease. The “stepped” profile of PB amount >7.5nm still be find after linear oxidation. To reduce the AA top corner “stepped” profile, the post-HF treatment’s AA silicon exposed in following APM process. The AA top corner and silicon sidewall which with APM treatment is clipping suspect H2O2 oxidize silicon and NH4OH consume the oxide caused. This profile made the region of exposed silicon to be deficient and pointed in AA geometry of silicon corner. The pointed AA top corner profile is unhelpful for corner rounding radius improvement, so the key factor of AA top rounding profile is corner silicon loss controller. In order to reduce the corner silicon loss amount, using H2O2 to replace the APM and dilute HF concentration to do oxide PB. This optimistic experience will be expected lower the exposed corner silicon consumption and corner rounding radius improvement. According oxide PB amount 5nm and 7.5nm comparison in 0.49%HF, the corner radius reduced 0.1nm when the PB increased. Nonetheless, HF concentration changed from 0.49% to 0.1% and H2O2 addition, the corner radius can be improved 0.3nm and 0.7nm. This result proved that the corner silicon profile of PB >5nm will be damaged in concentrated HF wet etch. Change to dilute HF concentration will reduce corner silicon loss and enable to recover corner silicon which with “stepped” profile by additional H2O2 treatment. As the higher oxide PB amount the pad oxide PB rate will become lower cause that without oxide protected corner silicon will be damaged and result in “stepped” profile. Nevertheless, using dilute HF can lower corner silicon loss and reduce the silicon erosion which without oxide protected. Additional H2O2 treatment introduced the rounding and smooth profile. The relationship between pad oxide PB and AA top corner rounding is established in STI process. The AA top corner radius of oxide PB amount 5nm can be improved 2.6nm compare to without PB process. When oxide PB amount >5nm the corner radius is decreased. The decreasing corner radius come from higher oxide PB amount that without oxide protected corner silicon will be damaged. This phenomenon result in “stepped” profile with difference curvature and corner radius decreasing. Dilute HF with H2O2 treatment is demonstrated that it is beneficial to reduce and recover the corner damaged. Figure 1

Microfabricated Vapor Cells with Reflective Sidewalls for Chip Scale Atomic Sensors.

We investigate the architecture of microfabricated vapor cells with reflective sidewalls for applications in chip scale atomic sensors. The optical configuration in operation is suitable for both one-beam and two-beam (pump & probe) schemes. In the miniaturized vapor cells, the laser beam is reflected twice by the aluminum reflectors on the wet etched 54.7° sidewalls to prolong the optical length significantly, thus resulting in a return reflectance that is three times that of bare silicon sidewalls. To avoid limitations faced in the fabrication process, a simpler, more universal and less constrained fabrication process of microfabricated vapor cells for chip scale atomic sensors with uncompromised performance is implemented, which also decreases the fabrication costs and procedures. Characterization measurements show that with effective sidewall reflectors, mm3 level volume and feasible hermeticity, the elongated miniature vapor cells demonstrate a linear absorption contrast improvement by 10 times over the conventional micro-electro-mechanical system (MEMS) vapor cells at ~50 °C in the rubidium D1 absorption spectroscopy experiments. At the operating temperature of ~90 °C for chip scale atomic sensors, a 50% linear absorption contrast enhancement is obtained with the reflective cell architecture. This leads to a potential improvement in the clock stability and magnetometer sensitivity. Besides, the coherent population trapping spectroscopy is applied to characterize the microfabricated vacuum cells with 46.3 kHz linewidth in the through cell configuration, demonstrating the effectiveness in chip scale atomic sensors.

Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

Effects of Added Mass on Lead-Zirconate-Titanate Thin-Film Microactuators in Aqueous Environments

In this paper, we conduct experimental, theoretical, and numerical studies of a lead-zirconate-titanate (PZT) thin-film microactuator probe submerged in water. The major component of the actuator is a PZT diaphragm anchored on four silicon sidewalls. There is also silicon residue at the juncture of the diaphragm and the sidewalls due to imperfect etching processes. In the experimental study, frequency response functions of actuator displacement are measured via a laser Doppler vibrometer and a spectrum analyzer. The measurements show that the first natural frequency of the microactuator reduces from 80 kHz in air to 20 kHz when the microactuator is submerged in water. A viable explanation is that the surrounding water induces significant added mass to the microactuator. Estimation of the added mass based on theories in fluid mechanics successfully reconciles the predicted frequency to the vicinity of 20 kHz confirming the effects of added mass. Finite element models are also created to study how the silicon sidewalls and residue affect the added mass. Simulations show that presence of the sidewalls or residue would modify the fluid flow thus altering the added mass and natural frequency. In general, the finite element predictions agree well with the experimental measurements within 10% difference.

A Self-Aligned 45°-Tilted Two-Axis Scanning Micromirror for Side-View Imaging

This paper presents a two-axis electrothermal single-crystal-silicon micromirror that is tilted 45° out of plane on a silicon optical bench (SiOB). The SiOB provides mechanical support and electrical wiring to the tilted two-axis scanning mirror, as well as aligned trenches for assembling other optical components, such as optical fibers and GRIN lens. The pre-set tilting of the mirror plate is achieved via the bending of a set of stressed bimorph cantilevers. A stopper connected on the bending bimorphs reaches and is stopped by the adjacent silicon sidewall. The tilt angle can be precisely controlled by properly choosing the distance from the stopper to the silicon sidewall and the flexure bimorph length. The fabricated mirror plate is 0.72 mm $\times $ 0.72 mm and the footprint of the entire MEMS device is 2.22 mm $\times$ 1.25 mm. The measured maximum total optical scan angle of the mirror is approximately 40° in both $x$ -axis and $y$ -axis at only $5.5~V_{\mathrm{ dc}}$ . This technology will enable a new class of more compact microendoscopic optical imaging probes for in vivo early cancer detection. [2015-0315]

Oblique patterned etching of vertical silicon sidewalls

A method for patterning on vertical silicon surfaces in high aspect ratio silicon topography is presented. A Faraday cage is used to direct energetic reactive ions obliquely through a patterned suspended membrane positioned over the topography. The technique is capable of forming high-fidelity pattern (100 nm) features, adding an additional fabrication capability to standard top-down fabrication approaches.

Top-down fabrication optimisation of ZnO nanowire-FET by sidewall smoothing

This paper describes the optimisation of top-down fabrication process of the ZnO-based dual nanowire field effect transistors (NWFETs) based on the spacer method. The approach uses the top-down nanowire process with reduced sidewall roughness during pattern transfer to improve the electrical characteristics. The main feature of the process involves a reflow of the photoresist performed at a temperature of 130°C and dry oxidation of the etched silicon sidewalls. The process optimisation leads to a significant reduction of the root-mean-square (rms) roughness of the photoresist from 23.2nm to 3.6nm and the ZnO nanowire rms surface roughness from 11.2nm to 5.5nm. The ZnO-based NWFET fabricated with the resist reflow process operates in depletion mode with a threshold voltage of −6V, a subthreshold slope of 0.80V/decade, an on–off current ratio of 106, a transconductance of 5.9nS and field effect mobility of 7.7cm2/Vs.

Novel Silicon on Insulator Monolithic Active Pixel Structure With Improved Radiation Total Ionizing Dose Tolerance and Reduced Crosstalk Between Sensor and Electronics

This paper introduces an advanced silicon on insulator (SOI) monolithic active pixel structure that leaves small empty volumes (interspace structure) under the SOI electronics wafer to mitigate the back-gate effect and implements silicon sidewall around the complementary metal oxide semiconductor (CMOS) electronics. The interspaces are produced by etching gaps in the oxide grown on top of the sensor wafer (buried oxide, BOX) and aligned with the CMOS channels in the electronics wafer above. The silicon sidewall surrounding the CMOS electronics is connected to the conductor layer. Two-dimensional and three-dimensional physical level simulations are presented to compare this novel structure with the nested well structure and double SOI structure. The results demonstrate that the proposed design could eliminate radiation total ionizing dose effects and reduce the parasitic capacitance between the electronics and sensor. Besides, the impact of varying the applied bias voltage and the p-well dimension on charge collection efficiency has also been studied.

Laser light routing in an elongated micromachined vapor cell with diffraction gratings for atomic clock applications.

This paper reports on an original architecture of microfabricated alkali vapor cell designed for miniature atomic clocks. The cell combines diffraction gratings with anisotropically etched single-crystalline silicon sidewalls to route a normally-incident beam in a cavity oriented along the substrate plane. Gratings have been specifically designed to diffract circularly polarized light in the first order, the latter having an angle of diffraction matching the (111) sidewalls orientation. Then, the length of the cavity where light interacts with alkali atoms can be extended. We demonstrate that a longer cell allows to reduce the beam diameter, while preserving the clock performances. As the cavity depth and the beam diameter are reduced, collimation can be performed in a tighter space. This solution relaxes the constraints on the device packaging and is suitable for wafer-level assembly. Several cells have been fabricated and characterized in a clock setup using coherent population trapping spectroscopy. The measured signals exhibit null power linewidths down to 2.23 kHz and high transmission contrasts up to 17%. A high contrast-to-linewidth ratio is found at a linewidth of 4.17 kHz and a contrast of 5.2% in a 7-mm-long cell despite a beam diameter reduced to 600 μm.