Top-down fabrication optimisation of ZnO nanowire-FET by sidewall smoothing

Abstract

This paper describes the optimisation of top-down fabrication process of the ZnO-based dual nanowire field effect transistors (NWFETs) based on the spacer method. The approach uses the top-down nanowire process with reduced sidewall roughness during pattern transfer to improve the electrical characteristics. The main feature of the process involves a reflow of the photoresist performed at a temperature of 130°C and dry oxidation of the etched silicon sidewalls. The process optimisation leads to a significant reduction of the root-mean-square (rms) roughness of the photoresist from 23.2nm to 3.6nm and the ZnO nanowire rms surface roughness from 11.2nm to 5.5nm. The ZnO-based NWFET fabricated with the resist reflow process operates in depletion mode with a threshold voltage of −6V, a subthreshold slope of 0.80V/decade, an on–off current ratio of 106, a transconductance of 5.9nS and field effect mobility of 7.7cm2/Vs.