Silicon Quantum Dot Spin Qubits Research Articles

Designing Globally Time-Optimal Entangling Gates Using Geometric Space Curves

High-fidelity entangling gates are essential for quantum computation. Currently, most approaches to designing such gates are based either on simple, analytical pulse waveforms or on ones obtained from numerical optimization techniques. In both cases, it is typically not possible to obtain a global understanding of the space of waveforms that generate a target gate operation, which can make it challenging to identify globally time-optimal waveforms that respect amplitude and bandwidth constraints. Here, we show that in the case of weakly coupled qubits, it is possible to find all pulses that implement a target entangling gate in near-minimal time. We do this by mapping quantum evolution onto geometric space curves. We derive the minimal conditions these curves must satisfy in order to guarantee a gate with a desired entangling power is implemented. Pulse waveforms are extracted from the curvatures of these curves. We illustrate our method by designing fast, cnot-equivalent entangling gates for silicon quantum dot spin qubits with fidelities exceeding 99 %. We show that fidelities can be further improved while maintaining low bandwidth requirements by using geometrically derived pulses as initial guesses in numerical optimization routines.

A Silicon Surface Code Architecture Resilient Against Leakage Errors

Spin qubits in silicon quantum dots are one of the most promising building blocks for large scale quantum computers thanks to their high qubit density and compatibility with the existing semiconductor technologies. High fidelity single-qubit gates exceeding the threshold of error correction codes like the surface code have been demonstrated, while two-qubit gates have reached 98% fidelity and are improving rapidly. However, there are other types of error --- such as charge leakage and propagation --- that may occur in quantum dot arrays and which cannot be corrected by quantum error correction codes, making them potentially damaging even when their probability is small. We propose a surface code architecture for silicon quantum dot spin qubits that is robust against leakage errors by incorporating multi-electron mediator dots. Charge leakage in the qubit dots is transferred to the mediator dots via charge relaxation processes and then removed using charge reservoirs attached to the mediators. A stabiliser-check cycle, optimised for our hardware, then removes the correlations between the residual physical errors. Through simulations we obtain the surface code threshold for the charge leakage errors and show that in our architecture the damage due to charge leakage errors is reduced to a similar level to that of the usual depolarising gate noise. Spin leakage errors in our architecture are constrained to only ancilla qubits and can be removed during quantum error correction via reinitialisations of ancillae, which ensure the robustness of our architecture against spin leakage as well. Our use of an elongated mediator dots creates spaces throughout the quantum dot array for charge reservoirs, measuring devices and control gates, providing the scalability in the design.

Silicon qubit fidelities approaching incoherent noise limits via pulse engineering

The performance requirements for fault-tolerant quantum computing are very stringent. Qubits must be manipulated, coupled, and measured with error rates well below 1%. For semiconductor implementations, silicon quantum dot spin qubits have demonstrated average single-qubit Clifford gate error rates that approach this threshold, notably with error rates of 0.14% in isotopically enriched $^{28}$Si/SiGe devices. This gate performance, together with high-fidelity two-qubit gates and measurements, is only known to meet the threshold for fault-tolerant quantum computing in some architectures when assuming that the noise is incoherent, and still lower error rates are needed to reduce overhead. Here we experimentally show that pulse engineering techniques, widely used in magnetic resonance, improve average Clifford gate error rates for silicon quantum dot spin qubits to 0.043%,a factor of 3 improvement on previous best results for silicon quantum dot devices. By including tomographically complete measurements in randomised benchmarking, we infer a higher-order feature of the noise called the unitarity, which measures the coherence of noise. This in turn allows us to theoretically predict that average gate error rates as low as 0.026% may be achievable with further pulse improvements. These fidelities are ultimately limited by Markovian noise, which we attribute to charge noise emanating from the silicon device structure itself, or the environment.

Integrated silicon qubit platform with single-spin addressability, exchange control and single-shot singlet-triplet readout

Silicon quantum dot spin qubits provide a promising platform for large-scale quantum computation because of their compatibility with conventional CMOS manufacturing and the long coherence times accessible using 28Si enriched material. A scalable error-corrected quantum processor, however, will require control of many qubits in parallel, while performing error detection across the constituent qubits. Spin resonance techniques are a convenient path to parallel two-axis control, while Pauli spin blockade can be used to realize local parity measurements for error detection. Despite this, silicon qubit implementations have so far focused on either single-spin resonance control, or control and measurement via voltage-pulse detuning in the two-spin singlet–triplet basis, but not both simultaneously. Here, we demonstrate an integrated device platform incorporating a silicon metal-oxide-semiconductor double quantum dot that is capable of single-spin addressing and control via electron spin resonance, combined with high-fidelity spin readout in the singlet-triplet basis.