Silicon-oxide-nitride-oxide-silicon Research Articles

Performance Comparison of SONOS-Type UV TD Sensor Using Indium Tin Oxide-Aluminum Oxide-Zirconia Aluminum Oxide-Silicon Oxide-Silicon and Indium Tin Oxide-Aluminum Oxide-Hafnium Aluminum Oxide-Silicon Oxide-Silicon

This study compares the performance of two types of capacitive devices, indium tin oxide-aluminum oxide-zirconia aluminum oxide-silicon oxide-silicon (IAZAOS) and indium tin oxide-aluminum oxide-hafnium aluminum oxide-silicon oxide-silicon (IAHAOS), as silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory (NVM) total dose of ultraviolet radiation (UV TD) sensors. Results show that IAZAOS with zirconia aluminum oxide as the charge-trapping layer outperforms IAHAOS with hafnium aluminum oxide for a UV TD sensor. After exposure to UV TD irradiation of 100 mW·s/cm2, the threshold voltage (VT) change of IAZAOS is almost 1.25 times that of IAHAOS. The study also found that annealing can significantly improve the response performance of IAZAOS UV TD sensors. Furthermore, IAZAOS devices with partially smaller nanocrystals in the charge-trapping layer greatly enhance the response of SONOS-type UV TD sensors. The study also compared the constant voltage stress-induced leakage current (CVSILC) and found that the CVSILC for annealed IAZAOS devices is 1000 times smaller than that of IAHAOS devices. Moreover, the IAZAOS-I2Z2 exhibits a superior performance regarding irradiation/refresh cycle endurance as compared to the IAHAOS-I2H1 device. These findings suggest that IAZAOS capacitive devices have superior performance and potential for use in SONOS-type UV TD sensors.

Cryogenic Storage Memory with High‐Speed, Low‐Power, and Long‐Retention Performance

AbstractCryogenic‐computing draws attention due to its variety of applications such as cloud‐computing, aerospace electronics, and quantum computing. Low temperature (e.g., 77 K) enables higher switching speed, improved reliability, and suppressed noise. Although cryogenic dynamic random‐access memory is studied, the cryogenic NAND flash is not explored intensively. Herein, a cryogenic storage memory based on the charge‐trap mechanism is reported. By removing the tunneling oxide from the conventional silicon/oxide/nitride/oxide/silicon (SONOS)‐type flash memory (therefore becoming silicon/oxide/nitride/silicon (SONS)), high‐speed and low‐power operation is aimed to be achieved while relieved from poor retention issue thanks to the cryogenic environment. The FinFET‐structured SONS memory device is demonstrated experimentally with gate length of 20–30 nm, which can achieve the retention issue (>10 years) with low voltage (≈6.5 V) and high speed (≈5 µs) operation at 77 K. To have a holistic system‐level evaluation, benchmark simulation of an interface between a host microprocessor and solid‐state‐drive is conducted, considering the refrigerator cooling cost and the heat loss via cables across two temperatures (300 and 77 K). The results show that the SONS‐type cryogenic storage system shows over 81% improvement in both latency and power, compared to the SONOS counterpart located at cryogenics.

Numerical Simulation of Trapped Hole Lateral Migration and Induced Threshold Voltage Retention Loss in a SONOS Flash Memory

We establish a one-dimensional transient simulation to study trapped hole lateral migration in the silicon nitride of a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory cell. In our model, the nitride traps have a continuous energy distribution. Trapped hole emissions to the valence band of the silicon nitride, free hole recapture into the nitride traps, and hole drift-diffusion in the valance band are included in the simulation. Two major trapped hole emission processes, thermally assisted tunneling (ThAT) and the Frenkel-Poole emission are considered. We simulate trapped hole lateral migration in a SONOS cell with program electrons stored at the source side and erase holes at the drain side. Our simulation shows that the ThAT is a dominant transport mechanism for trapped hole lateral migration in retention. We also simulate a threshold voltage (Vt) retention loss due to trapped hole lateral migration at different program levels. The trend of the simulated Vt retention loss is consistent with the measurement result.

Design of auto-store circuit for nvSRAM with SONOS access transistor

In this paper, an auto-store circuit that can perform a store and restore operation of non-volatile SRAM (nvSRAM) with access transistor whose gate stack is Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is designed. The suggested auto-store circuit is consisted by two small circuit parts of a store and restore circuit. The store circuit moves data in SRAM cell into SONOS device before power turns off while a restore circuit recalls the data to SRAM cell when the power is resupplied. When the nvSRAM replaces its conventional access transistor with the SONOS flash memory device, higher word line voltage is needed for a store operation. It demands much energy and additional voltage source to store a data. To overcome this disadvantage, the capacitor component is added in the store and restore circuit which is charged during the normal operation mode. At the moment of the power-off, the store circuit discharges the capacitors and applies higher voltage to the word line for the store operation. When the power is supplied again, the restore circuit discharges the capacitor and applies pre-charge voltage and restore the data to the bit line and word line. The simulation results show that the suggested auto store circuit can perform the store, restore operation in the sudden power off without an additional voltage source.

Non-volatile flash memory based on Van der Waals gate stack using bandgap tunability of hexagonal boron nitride

Electronic devices based on two-dimensional (2D) materials have extended their applications to non-volatile flash memory devices. The gate stack is a key structure in flash memory devices, and the conventional silicon-oxide-nitride-oxide-silicon (SONOS) structure has been widely applied. In this study, we propose a van der Waals (vdW) gate stack based on graphene, molybdenum disulfide (MoS2), and hexagonal boron nitride (hBN) for next-generation flash memory devices. Owing to the bandgap tunability of hBN by functionalization, hBN is capable of forming a tunneling layer, charge trap layer, and blocking layer with different bandgaps, resulting in a suitable energy band offset for program/erase operations and charge storage. This study on the vdW gate stack of MoS2/tunneling hBN/charge trap hBN/blocking hBN/graphene was carried out through technology computer-aided design (TCAD) simulation. The trapped charge density and threshold voltage (Vth) shift were investigated for different bandgaps of the hBN layers. Moreover, the pulse width and cycle were varied to reveal the charge-trapping behavior for further applications.

Physical Compact Model for Three‐Terminal SONOS Synaptic Circuit Element

A well‐posed physics‐based compact model for a three‐terminal silicon–oxide–nitride–oxide–silicon (SONOS) synaptic circuit element is presented for use by neuromorphic circuit/system engineers. Based on technology computer aided design (TCAD) simulations of a SONOS device, the model contains a nonvolatile memristor with the state variable QM representing the memristor charge under the gate of the three‐terminal element. By incorporating the exponential dependence of the memristance on QM and the applied bias V for the gate, the compact model agrees quantitatively with the results from TCAD simulations as well as experimental measurements for the drain current. The compact model is implemented through VerilogA in the circuit simulation package Cadence Spectre and reproduces the experimental training behavior for the source–drain conductance of a SONOS device after applying writing pulses ranging from −12 V to +11 V, with an accuracy higher than 90%.

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory

We demonstrate SONOS (silicon-oxide-nitride-oxide-silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt; 10\times $ </tex-math></inline-formula> gain in energy efficiency over state-of-the-art digital and analog inference accelerators.

Improved Hopfield Network Optimization Using Manufacturable Three-Terminal Electronic Synapses

We illustrate novel optimization techniques via simulations for Hopfield networks constructed from manufacturable three-terminal Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic circuit elements. We first present a computationally-light, memristor-based, highly accurate static compact model for the SONOS synapses used in our simulations. We then show how to exploit analog errors in programming resistances and current leakage, and the continuous tunability of the SONOS synapses to enable transient chaotic group dynamics, to accelerate the convergence of a Hopfield network. We project improvements in energy consumption and time to solution relative to existing CPUs and GPUs by at least 4 orders of magnitude, and also exceed the projected performance of two-terminal memristor-based crossbars in addition to a 100-fold increase in error-resilient array size (i.e. problem size).

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory.

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

Process effect analysis on nitride trap distribution in silicon-oxide-nitride-oxide-silicon flash memory based on charge retention model

This paper analyzes data retention characteristics to determine process effects on the trap energy distribution of silicon nitride in silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. Nitride films were prepared by low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). PEVCD films embedded with silicon nanocrystals (Si-NCs) were also compared. The flat band voltage shift in the programmed device was measured at high temperatures to observe the thermal excitation of electrons from the nitride traps in retention mode. The trap energy distribution was extracted using the charge decay rates, and the experimental results showed that nitride fabricated by PECVD has a shallower trap than nitride fabricated by LPCVD. In nitride with Si-NCs, increased trap sites were observed in the range of 1.14 eV to 1.24 eV.

Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping

In this paper, it is shown that the erase efficiency of the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type nonvolatile charge trapping memory (CTM) is greatly improved by adjusting boron doping. Tunnel FET (TFET) based SONOS memory, which has p-type at source side, is superior to MOSFET based SONOS memory in terms of hole supplement and erase speed. In order to discover the specific physical reasons of this erase speed enhancement, MOSFET based SONOS memory devices with different body doping concentration are additionally investigated. As a result, it is found that the more hole supplement from source side in TFET and body side in MOSFET accelerates the erase speed and erase speed enhancement can be realized by utilizing boron doping. Furthermore, erase speed depending on device geometry, in terms of source-to-gate overlap length and gate length, is also analyzed. Interestingly, it is demonstrated that source overlap technique, which has been implemented for suppression of ambipolar current, is also possible to accelerate erase speed.

Modeling and Verification of Interface and Bulk Trap Level Density Extraction in SONOS Memory Charge Trapping Layer

Retention characteristics of silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory are affected by properties such as energy level and spatial location. In this study, a model was presented that separately evaluated the bulk and interface trap level density distributions in the SONOS nonvolatile memory charge trapping layer (CTL). This model is proposed in the form of a first-order function of nitride thick XN, so the bulk and interface trap densities, gbulk and ginterface, respectively, can be extracted from the slope and y-intercept. Measurements were performed on various thickness samples. For verification, CTL1 and CTL2 were formed by different processes. The extracted CTL1 gbulk and ginterface are on the order of 1017 cm−3 and 1011 cm−2, and the CTL2 gbulk and ginterface are of the order of 1018 cm−3 and 1012 cm−2, respectively. Using this model, a direction to improve the SONOS device retention characteristics can be suggested.

Non-Volatile Photonic Memory Based on a SAHAS Configuration

The non-volatile memory is a crucial functionality for a wide range of applications in photonic integrated circuits, however, it still poses a challenge in silicon photonic technology. This problem has been overcome in the microelectronic industry by using SONOS (silicon-oxide-nitride-oxide-silicon) memory cells, in which the non-volatility is enabled by a dielectric trapping layer such as silicon nitride. Analogously, in this work, a similar approach in which the nitride has been replaced by a hafnium oxide layer, named as SAHAS configuration, is proposed for enabling a programmable erasable photonic memory fully compatible with the silicon platform. The structure features an efficient performance with writing and erasing times of 100 μs, retention times over 10 years and energy consumption in the pJ range, which improve the current SONOS or floating gate based photonic approaches that exploit the plasma dispersion effect in silicon. The proposed non-volatile photonic memory device shows an extinction ratio above 12 dB and insertion losses below 1 dB in a compact footprint. In addition, because the memory is optically read, ultrafast access times in the picosecond range are also achieved.

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OXb) and channel/OXb regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I ON). The device structure is constructed using Sentaurus TCAD tools, and I D–V G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec−1, while the I ON was 3.02 × 10−4 A. The memory window was 2.95 V, showing more dependence on programming pulse height (V gp) than erasing pulse height (V ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 108 s (10 years) storage.

Ionizing Radiation Effects in SONOS-Based Neuromorphic Inference Accelerators

We evaluate the sensitivity of neuromorphic inference accelerators based on silicon-oxide-nitride-oxide-silicon (SONOS) charge trap memory arrays to total ionizing dose (TID) effects. Data retention statistics were collected for 16 Mbit of 40-nm SONOS digital memory exposed to ionizing radiation from a Co-60 source, showing good retention of the bits up to the maximum dose of 500 krad(Si). Using this data, we formulate a rate-equation-based model for the TID response of trapped charge carriers in the ONO stack and predict the effect of TID on intermediate device states between “program” and “erase.” This model is then used to simulate arrays of low-power, analog SONOS devices that store 8-bit neural network weights and support in situ matrix-vector multiplication. We evaluate the accuracy of the irradiated SONOS-based inference accelerator on two image recognition tasks - CIFAR-10 and the challenging ImageNet data set - using state-of-the-art convolutional neural networks, such as ResNet-50. We find that across the data sets and neural networks evaluated, the accelerator tolerates a maximum TID between 10 and 100 krad(Si), with deeper networks being more susceptible to accuracy losses due to TID.

Cryogenic characterisation of 55 nm SONOS charge‐trapping memory in AC and DC modes

The electrical responses of 55 nm silicon–oxide–nitride–oxide–silicon (SONOS) memory cells have been investigated under cryogenic conditions, and the changes of the read curves of SONOS in AC mode (programmed/erased with pulse voltage) and DC mode (programmed/erased with direct voltage sweeping) at low temperatures are compared. The experimental results show that with the decrease of temperature, the subthreshold swing of SONOS decreases, whereas the on-state current of SONOS increases. The difference in AC and DC operations causes the threshold voltage of the read curve to drift accordingly, leading to the different change in the memory window. However, in both modes of operations, the efficiencies of programming and erasing decrease at cryogenic temperatures. It is analysed that the reduction of programming efficiency at cryogenic temperatures is caused by the decrease in the quantity of pre-tunnelling electrons. The reduction in erasing efficiency is attributable to the suppression of the Poole–Frenkel effect at low temperatures, which makes it more difficult for electrons to be de-trapped.

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxide-nitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current ( $\text{I}_{\mathrm {off}}$ ). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the $\text{I}_{\mathrm {off}}$ caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

Investigation of Intra-Nitride Charge Migration Suppression in SONOS Flash Memory

In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N2 plasma treated on the silicon nitride is proposed. Experimental results show that the charge loss decreased in the plasma treated device after baking at 300 °C for 2 h. To extract trap density according to the location in the trapping layer, capacitance-voltage analysis was used and N2 plasma treatment was shown to be effective to restrain the interface trap formation between blocking oxide and silicon nitride. Moreover, from X-ray Photoelectron Spectroscopy, the reduction of Si-O-N bonding was observed.

NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

In this work, we investigate a promising technique for improving the performance of silicon-on-insulator (SOI) silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory cells with ground plane in buried oxide (GPB). The physical phenomena that potentially degrade the performance of NAND flash memory cells at lower gate length are controlled by selection of an appropriate NAND flash device architecture. The various attributes of SONOS memory cells with GPB are compared with conventional SOI SONOS memory devices. It is shown that at the scaled gate length of 25 nm, a flash memory cell with GPB limits the short channel effects and achieves ~ 103 times higher memory speed. The short channel performance is evaluated by considering subthreshold slope (SS) and drain-induced barrier lowering (DIBL) parameters, which show significant improvement in SS along with relatively lower DIBL values at lower gate lengths in SONOS cells with GPB. The results highlight that a ~ 1.3 times wider memory window and ~ 2.4 times higher retention can be obtained over a period of 10 years in a SONOS GPB device in comparison to the SOI SONOS memory device. The present work provides guidelines to design highly dense flash memory devices while achieving improved reliability without altering the gate stack.

Total Ionizing Dose Effects of 55-nm Silicon-Oxide-Nitride-Oxide-Silicon Charge Trapping Memory in Pulse and DC Modes**Supported by the National Natural Science Foundation of China under Grant No 616340084, the Youth Innovation Promotion Association of Chinese Academy of Sciences under Grant No 2014101, and the Austrian-Chinese Cooperative R&D Projects of International Cooperation Project of Chinese Academy of Sciences under Grant No 172511KYSB20150006.

The 60Co-γ ray total ionizing dose radiation responses of 55-nm silicon-oxide-nitride-oxide-silicon (SONOS) memory cells in pulse mode (programmed/erased with pulse voltage) and dc mode (programmed/erased with direct voltage sweeping) are investigated. The threshold voltage and off-state current of memory cells before and after radiation are measured. The experimental results show that the memory cells in pulse mode have a better radiation-hard capability. The normalized memory window still remains at 60% for cells in dc mode and 76% for cells in pulse mode after 300 krad(Si) radiation. The charge loss process physical mechanisms of programmed SONOS devices during radiation are analyzed.