Abstract

In this work, we investigate a promising technique for improving the performance of silicon-on-insulator (SOI) silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory cells with ground plane in buried oxide (GPB). The physical phenomena that potentially degrade the performance of NAND flash memory cells at lower gate length are controlled by selection of an appropriate NAND flash device architecture. The various attributes of SONOS memory cells with GPB are compared with conventional SOI SONOS memory devices. It is shown that at the scaled gate length of 25 nm, a flash memory cell with GPB limits the short channel effects and achieves ~ 103 times higher memory speed. The short channel performance is evaluated by considering subthreshold slope (SS) and drain-induced barrier lowering (DIBL) parameters, which show significant improvement in SS along with relatively lower DIBL values at lower gate lengths in SONOS cells with GPB. The results highlight that a ~ 1.3 times wider memory window and ~ 2.4 times higher retention can be obtained over a period of 10 years in a SONOS GPB device in comparison to the SOI SONOS memory device. The present work provides guidelines to design highly dense flash memory devices while achieving improved reliability without altering the gate stack.

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