Silicon-On-Nothing MOSFETs Research Articles

Gate electrode stacked source/drain SON trench MOSFET for biosensing application

This work inspects a dielectrically modulated (DM) stacked source/drain SiGe dual-metal trench gate silicon on nothing (SON) metal–oxide–semiconductor field-effect transistor (SiGe-DMTG SON MOSFET) biosensor to enhance the sensing capability of the device. A nano-cavity is implanted in the either side of gate area for immobilization of biomolecules which can modulate the gate capacitance and dielectric constant of the nanocavity area. Thus the device undergoes a threshold voltage shift which has a great impact on device sensitivity. So SiGe-DMTG SON MOSFET biosensor is proposed to identify the sensing performance of various analytes like Uricase (k = 1.54), Streptavidin (k = 2.1), Biotin (k = 2.63), 3-aminopropyltriethoxysilane (APTES) (k = 3.57) and protein (k = 8) using DM technique. The electrostatic properties of the neutral biomolecules such as electrostatic potential, electric field, On current, switching ratio, threshold voltage, On current sensitivity, threshold voltage sensitivity, and subthreshold performance of SiGe-DMTG SON MOSFET biosensor have been evaluated using 2D ATLAS device simulator. Further, the parasitic capacitances of the proposed biosensor has been investigated for different biomolecules in the nano-cavity region in order to observe the sensing performance of the device. From the result analysis it has been observed that for protein (k = 8), the proposed SiGe-DMTG SON MOSFET biosensor offers a threshold voltage sensitivity of 0.581 and On current sensitivity of 1.765. Apart from this, protein (k = 8) offers a strong threshold voltage shift of 104.8 mV with respect to k = 1 shows best suited for biosensing application.

Performance Investigation of Stepped Gate Recessed Channel SON (Silicon on Nothing) MOSFET for Improvement of SCEs

Performance Investigation of Stepped Gate Recessed Channel SON (Silicon on Nothing) MOSFET for Improvement of SCEs

Examining the Short Channel Characteristic and Performance of Triple Material Double Gate Silicon-on-Nothing Metal Oxide Semiconductor Field Effect Transistors with Grading Channel Concentration

A 2D surface potential analytical model of a channel with graded channel triple material double gate (GCTMDG) Silicon-on-Nothing (SON) MOSFET is proposed by intermixing the benefits of triple material in gate engineering and graded doping in the channel. The surface potential distribution function of the GCTMDG SON MOSFET is obtained by solving the Poisson's equation, applying suitable boundary conditions, and using a parabolic approximation method. It is seen in the proposed device that the Short Channel Effects (SCEs) are subdued due to the apprehensible step in the surface potential profile that screen the potential of the drain. The effects of the various device parameters are studied to check the merit of the device. For the validation of the proposed device, it is compared with the simulated results of ATLASTM, a device simulator from SILVACO.

Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET

A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects (SCEs). Two dimensional (2-D) Poisson's equation with proper boundary conditions has been solved considering the parabolic potential approximation. The model includes the calculations of threshold voltage, electric field and subthreshold swing. The impact of variation of the device parameters such as gate length ratios, gate metal work functions on the performance of the device has been examined and the results are compared to that of dual-material double gate (DMDG) Silicon-on-Insulator (SOI) MOSFETs. The calculated results obtained have been validated with the numerical simulation data obtained from ATLAS, a 2-D device simulator from SILVACO.

Comprehensive quantum mechanical modeling of short channel SON MOSFET with spatial composition grading of binary metal alloy gate electrode

In this present work, for the first time, carrier quantization effects are incorporated in a Work Function Engineered Gate (WFEG) Silicon-On-Nothing (SON) MOSFET where horizontal mole fraction of the binary metal alloy gate is varied continuously. A detailed analytical modeling of inversion charge for this novel structure has been presented based on the self-consistent solution of 2D Poisson’s equation and 1D Schrödinger equation. Deviation of threshold voltage due to quantization is added with the classical one to find the modified threshold voltage in quantum case. Finally the analytical expression for drain current in the inversion region is derived considering quantum effects and comparative analysis with the previous classical model is shown. Proposed analytical model is validated against the professional numerical device simulation tool ATLAS-2D, thereby ensuring the accuracy of our model.

Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Volatge Digital Applications

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

Quantum Analytical Model for Inversion Charge and Threshold Voltage of Short-Channel Dual-Material Double-Gate SON MOSFET

Our previous work analytically establishes that silicon-on-nothing (SON) is superior to silicon-on-insulator MOSFET because of its higher immunity to different short-channel effects and increased current driving capability. Moreover, it has also been shown that our analytical model agrees with various simulation results obtained from MEDICI, ATLAS 2-D, and so on. Because of the ultrathin device structure, classical models are not sufficient to determine accurately potential profile, threshold voltage, or charge inversion phenomena for dual-material double-gate (DMDG) SON MOSFET. Hence, in this paper, for the first time, carrier quantization arising due to the ultrathin body has been included to develop an analytical model for ultrathin low-dimensional DMDG SON structure. The 2-D Poisson and 1-D Schrodinger equations have been solved under the dual-material front gate to find the overall potential and inversion charge profile. The deviation of the quantum threshold voltage from the classical one has been calculated and added to the classical threshold voltage to get its quantum counterpart. The proposed model has also been validated against the numerical device simulator ATLAS 2-D.

Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application

An overall performance comparison analysis based on 2-D Poisson's equation solution has been presented here both for silicon-on-insulator (SOI) and silicon-on-nothing (SON) MOSFET structures. In this paper, for the first time, an idea of work function engineering with continuous horizontal mole fraction variation in a binary alloy gate has been proposed and implemented analytically to reduce rolloff in threshold voltage for SON MOSFET, thereby improving its performance over single-gate SON structures. Analytical model-based simulation verified that SON is superior over SOI MOSFET due to its higher immunity to different short-channel effects and increased current driving capability. Our results are found to be in good agreement with simulation results, thereby verifying the accuracy of the proposed analytical model.

(Invited) Si, SiGe, Ge, and III-V Semiconductor Nanomembranes and Nanowires Enabled by SiGe Epitaxy

SiGe epitaxy in conjuction with selective etching lends itself as an excellent method for manufacturing of nanomembranes and nanowires for a variety of semiconductor materials and nano-geometries. Early device application of this technique has been demonstrated for the device architecture of Silicon-On-Nothing (SON) MOSFET and localized SON MOSFET allowing accommodation of a SOI-type MOSFET on a bulk Si wafer. In the meantime, this approach has been successfully extended to multichannel and multi-nanowire devices. Together with the availability of thin Ge layers (e.g. by virtue of Ge condensation), SiGe epitaxy opens up the possibility of a heterogenous co-integration of high efficiency III-V multijunction solar cells, III-V complementary logic, thermovoltaic device structures, lasers, modulators and detectors with Si-based electronics collocated on the same Si substrate. SiGeC epitaxial layers offer an additional engineering window for lattice mismatch and stress control, as well for achieving desirable selectivities of the required selective etches. Furthermore, the nanomembranes and nanowires made available by SiGe epitaxy and selective etches on ubiquitous Si substrates are excellent vehicles for exploration of the differences between the material properties of 3D (bulk)) and 2D (nanomembranes) and 1D (nanowire) systems.

Dual-Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part II: Impact of Gate-Dielectric Material Engineering

Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M1</sub> / L ratio as 1/2 amalgamates the advantages of using a high metal work-function gate M1 and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high-k/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M1</sub> /L ratio as 1/2, proving to be the best choice among various L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M1</sub> /L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -gain relationship.

Study of SiO 2/Si interface properties of SON MOSFETs by random telegraph signal and charge pumping measurements

In this paper, we report a comprehensive study of the gate oxide/channel interface properties of submicron MOSFETs integrated in a SON technology [Jurczak M, et al. Silicon-On-Nothing (SON) – an innovative process for advanced CMOS. IEEE-TED 2000;47:2179, Monfray S, et al. First 80 nm SON (Silicon On Nothing) transistor with perfect morphology and high electrical performance. IEDM Tech Dig 2001:645, Monfray S, et al. SON (Silicon-On-Nothing) technological CMOS platform: Highly performant devices and SRAM cells. IEDM Tech Dig 2004:635]. The interface state density ( D it) is determined by two-levels charge pumping analysis on long-channel partially-SON transistors where the Si-channel is in contact with the substrate. On short-channel SON transistors, where the Si-channel is completely isolated from the substrate, we were able to determine the characteristics of individual trap located inside the gate oxide using random telegraphic signal (RTS) analysis: activation energy and distance from the SiO 2/Si interface. The experimental RTS results demonstrate the validity of the Shockley–Read–Hall (SRH) statistics for a single trap activity and conclusively prove that SON technology does not introduce additional defects at the gate oxide/channel interface when compared to CMOS technology.

Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity

In this paper, “true” Silicon-On-Nothing (SON) MOSFETs fabricated by a new technique, consisting in Si layer transfer over a pre-etched cavity, are investigated. The process has no potential limitation with regards to the device dimensions as well as to the thicknesses of Si film and so-called “nothing” layers. Comparing to single-gate (SG) fully-depleted (FD) SOI MOSFETs fabricated on the same wafer, improved electrical characteristics of SON MOSFETs are demonstrated. Self-heating effect, which can be considered as the main drawback of SON devices, is experimentally addressed for the first time. Finally, the source-to-drain coupling through the substrate is demonstrated to be practically suppressed in such device architecture.

Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation

In this paper, a method to fabricate Silicon-on-Nothing (SON) MOSFETs using H+ and He+ co-implantation is presented. The technique is compatible with conventional CMOS technology and its feasibility has been experimentally demonstrated. SON MOSFETs with 50nm gate length have been fabricated. Compared with the corresponding bulk MOSFETs, the SON MOSFETs show higher on current, reduced leakage current and lower subthreshold slope.

Silicon-on-Nothing MOSFETs: Performance, Short-Channel Effects, and Backgate Coupling

Silicon-on-nothing (SON) transistors with gate length varying from 0.25 /spl mu/m down to 80 nm exhibit excellent performance and scalability. The silicon-on-insulator (SOI)-like architecture with thin fully depleted Si film and ultrathin buried oxide results in attenuated short-channel effects (charge sharing, DIBL and fringing fields), high current, and electron mobility. A new model accounts for the intrinsic mechanisms of operation in SON MOSFETs: i) substrate depletion governed by source and drain via doping modulation, ii) relatively low coupling between the front- and backgates, iii) role of ultrathin buried oxide. The proposed model reproduces the variations of the threshold voltage and subthreshold swing and is useful for further device optimization.